Datasheet
Datasheet, Volume 2 491
Processor Uncore Configuration Registers
4.4.3.6 BIOS_RESET_CPL—BIOS Reset Complete Register
This register is used as interface between BIOS and Pcode Bits in first Byte are written
by BIOS and read by Pcode Bits in second Byte are written by Pcode and read by BIOS
Expected sequence:
BIOS sets RST_CPL -> Pcode sets PCODE_INIT_DONE -> BIOS sets
RST_DRAM_CPL
BIOS should also clear the AutoAck bit, DMICTRL.AUTO_COMPLETE_PM
only after ensuring that the PCODE_INIT_DONE bit has been set to 1
by Pcode
BIOS_RESET_CPL
Bus: 1 Device: 10 Function: 1 Offset: 94h
Bit Attr
Reset
Value
Description
31:24 RO-FW 00h
Reserved for Pcode
Used to Facilitate handshake between Pcode and BIOS
Note: Attribute is RO-FW
23:16 RW1S 00h
Reserved for BIOS
Used to Facilitate handshake between BIOS and Pcode
Note: the Attribute is RW1S
15 RO-FW 0b
Pcode Init Done 7
Used to Facilitate handshake between Pcode and BIOS
14 RO-FW 0b
Pcode Init Done 6
Used to Facilitate handshake between Pcode and BIOS
13 RO-FW 0b
Pcode Init Done 5
Used to Facilitate handshake between Pcode and BIOS
12 RO-FW 0b
Pcode Init Done 4
Used to Facilitate handshake between Pcode and BIOS
11 RO-FW 0b
Pcode Init Done 3
Used to Facilitate handshake between Pcode and BIOS
Ack for Bit 3
10 RO-FW 0b
Pcode Init Done 2
Used to Facilitate handshake between Pcode and BIOS
Ack for Bit 2
9RO-FW 0b
Pcode Init Done 1
Used to Facilitate handshake between Pcode and BIOS
Ack for Bit 1
8RO-FW 0b
Pcode Init Done
Ack for Bit 0
This bit is used by Pcode to indicate to BIOS that Pcode has completed sampling of
the CSRs that BIOS configured and that Pcode is now ready to accept any multi-
socket power management transactions.
This bit cannot be set before the RESET_CPL bit is set by BIOS.
BIOS must first set the RESET_CPL bit and then poll on this bit, wait for it to be 1
before doing anything else - this is a blocking wait.
7RW1S0b
Reset CPL 7
Used to Facilitate handshake between BIOS and Pcode
6RW1S0b
Reset CPL 6
Used to Facilitate handshake between BIOS and Pcode
5RW1S0b
Reset CPL 5
Used to Facilitate handshake between BIOS and Pcode