Datasheet

Datasheet, Volume 2 49
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Processor Integrated I/O (IIO) Configuration Registers
3.2.4.4 PCISTS—PCI Status Register
1RW0b
Memory Space Enable
1 = Enables a PCI Express port’s memory range registers to be decoded as valid
target addresses for transactions from secondary side.
0 = Disables a PCI Express port’s memory range registers (including the
Configuration Registers range registers) to be decoded as valid target
addresses for transactions from secondary side. All memory accesses
received from secondary side are UR’ed.
0RO 0b
IO Space Enable
This bit controls a device's response to I/O Space accesses. When this bit is 0, it
disables the device response. When this bit is 1, it allows the device to respond to
I/O space accesses.
The state after RST# is 0. NTB does not support I/O space accesses. Hardwired to
0.
PCISTS
Bus: 0 Device: 0 Function: 0 Offset: 06h
Bus: 0 Device: 1 Function: 0–1 Offset: 06h
Bus: 0 Device: 2 Function: 0–3 Offset: 06h
Bus: 0 Device: 3 Function: 0–3 Offset: 06h
Bit Attr
Reset
Value
Description
15 RW1C 0b
Detected Parity Error
This bit is set by a root port when it receives a packet on the primary side with an
uncorrectable data error (including a packet with poison bit set) or an
uncorrectable address/control parity error. The setting of this bit is regardless of
the Parity Error Response bit (PERRE) in the PCICMD register.
14 RW1C 0b
Signaled System Error
1 = The root port reported fatal/non-fatal (and not correctable) errors it detected
on its PCI Express interface to the IIO core error logic (which might
eventually escalate the error through the ERR[2:0] pins or message to
processor core or message to PCH). The SERRE bit in the PCICMD register
must be set for a device to report the error in the IIO core error logic.
Software clears this bit by writing a 1 to it. This bit is also set (when SERR
enable bit is set) when a FATAL/NON-FATAL message is forwarded to the IIO
core error logic. IIO internal core errors (like parity error in the internal
queues) are not reported using this bit.
0 = The root port did not report a fatal/non-fatal error.
13 RW1C 0b
Received Master Abort
This bit is set when a root port experiences a master abort condition on a
transaction it mastered on the primary interface (uncore internal bus).
Note that certain errors might be detected right at the PCI Express interface and
those transactions might not propagate to the primary interface before the error is
detected (for example, accesses to memory above TOCM in cases where the PCIe
interface logic itself might have visibility into TOCM). Such errors do not cause this
bit to be set, and are reported using the PCI Express interface error bits
(secondary status register).
Conditions that cause bit 13 to be set, include:
• Device receives a completion on the primary interface (internal bus of uncore)
with Unsupported Request or master abort completion Status. This includes
UR status received on the primary side of a PCI Express port on peer-to-peer
completions also.
PCICMD
Bus: 0 Device: 0 Function: 0 Offset: 04h
Bus: 0 Device: 1 Function: 0–1 Offset: 04h
Bus: 0 Device: 2 Function: 0–3 Offset: 04h
Bus: 0 Device: 3 Function: 0–3 Offset: 04h
Bit Attr
Reset
Value
Description