Datasheet

Processor Uncore Configuration Registers
488 Datasheet, Volume 2
4.4.3 PCU1 Registers
4.4.3.1 SSKPD—Sticky Scratchpad Data Register
This register holds 64 writable bits with no functionality behind them. It is for the
convenience of BIOS and graphics drivers.
4.4.3.2 C2C3TT—C2 to C3 Transition Timer Register
Processor Usage – This register is being repurposed for the processor. Pcode will read
the value from this register and load it into a firmware timer. The timer is armed when
exiting PC3, and a status bit is set when the timer expires. The status bit serves as a
gate for entering PC3.
BIOS can update this value during run-time.
Unit for this register is usec. So we have a range of 0-4095 us.
Processor usage – This register contains the initial snoop timer (pop-down) value. BIOS
can update this value during run-time.
PCODE will sample this register at slow loop. If the value has changed since the
previous sample and in addition there is no valid Hystereris parameter (HYS) from a
previous PM_DMD or PM_RSP message, then PCODE will configure
IMPH_CR_SNP_RELOAD[LIM] with this value.
SSKPD
Bus: 1 Device: 10 Function: 1 Offset: 6Ch
Bit Attr
Reset
Value
Description
63:0 RWS
000000
000000
0000h
Scratchpad Data
4 WORDs of data storage.
C2C3TT
Bus: 1 Device: 10 Function: 1 Offset: 74h
Bit Attr
Reset
Value
Description
31:12 RV 0h Reserved
11:0 RW 32h
Pop Down Initialization Value
Value in micro-seconds.