Datasheet

Processor Uncore Configuration Registers
486 Datasheet, Volume 2
4.4.2.20 PRIP_TURBO_PWR_LIM—Primary Plane Turbo Power 
Limitation Register
This register is used by BIOS/OS/Integrated Graphics Driver/CPM Driver to limit the
power budget of the Primary Power Plane.
The overall package turbo power limitation is controlled by PKG_TURBO_POWER_LIMIT.
PRIP_TURBO_PWR_LIM
Bus: 1 Device: 10 Function: 0 Offset: F0h
Bit Attr
Reset
Value
Description
31 RW-KL 0b
Primary Plane Power Limit Lock
When set, all settings in this register are locked and are treated as Read Only.
30:24 RV 0h Reserved
23:17 RW-L 00h
Control Time Windows
x = CTRL_TIME_WIN[23:22]
y = CTRL_TIME_WIN[21:17]
The timing interval window is Floating Point number given by 1.x * power(2,y).
The unit of measurement is defined in
PACKAGE_POWER_SKU_UNIT_MSR[TIME_UNIT].
The maximal time window is bounded by
PACKAGE_POWER_SKU_MSR[PKG_MAX_WIN]. The minimum time window is
zero.
16 RW-L 0b
Power plane clamping limitation over TDP setting
Power plane Clamping limitation over TDP setting
15 RW-L 0b
Power Limitation Control Enable
This bit must be set in order to limit the power of the IA cores power plane.
0 = IA cores power plane power limitation is disabled
1 = IA cores power plane power limitation is enabled
14:0 RW-L 0000h
IA Cores Power Plane Power Limitation
This is the power limitation on the IA cores power plane.
The unit of measurement is defined in
PACKAGE_POWER_SKU_UNIT_MSR[PWR_UNIT].