Datasheet

Datasheet, Volume 2 481

Processor Uncore Configuration Registers
4.4.2.11 PP0_Any_Thread_Activity—PP0_Any_Thread_Activity Register
This register will count the BCLK cycles in which at least one of the IA cores was active.
This is a 32 bit accumulation done by PCU hardware. Values exceeding 32b will wrap
around.
4.4.2.12 PP0_Efficient_Cycles—Power Plane 0 Efficient Cycles Register
This register will store a value equal to the product of the number of BCLK cycles in
which at least one of the IA cores was active and the efficiency score calculated by the
PCODE. The efficiency score is a number between 0 and 1 that indicates the IA’s
efficiency.
This is a 32 bit accumulation done by P-code to this register out of the PUSH-BUS.
Values exceeding 32b will wrap around.
This value is used in conjunction with PP0_ANY_THREAD_ACTIVITY to generate
statistics for software.
4.4.2.13 PP0_Thread_Activity—Power Plane 0 Thread Activity Register
This register will store a value equal to the product of the number of BCLK cycles and
the number of IA threads that are running. This is a 32-bit accumulation done by PCU
haredware. Values exceeding 32b will wrap around.
This value is used in conjunction with PP0_ANY_THREAD_ACTIVITY to generate
statistics for SW.
PP0_Any_Thread_Activity
Bus: 1 Device: 10 Function: 0 Offset: B4h
Bit Attr
Reset
Value
Description
31:0 RO-V
000000
00h
DATA
Number of Cycles
PP0_Efficient_Cycles
Bus: 1 Device: 10 Function: 0 Offset: B8h
Bit Attr
Reset
Value
Description
31:0 RO-V
000000
00h
DATA
Number of Cycles
PP0_Thread_Activity
Bus: 1 Device: 10 Function: 0 Offset: BCh
Bit Attr
Reset
Value
Description
31:0 RO-V
000000
00h
DATA
Number of Cycles