Datasheet

Processor Integrated I/O (IIO) Configuration Registers
48 Datasheet, Volume 2
3.2.4.3 PCICMD—PCI Command Register
PCICMD
Bus: 0 Device: 0 Function: 0 Offset: 04h
Bus: 0 Device: 1 Function: 0–1 Offset: 04h
Bus: 0 Device: 2 Function: 0–3 Offset: 04h
Bus: 0 Device: 3 Function: 0–3 Offset: 04h
Bit Attr
Reset
Value
Description
15:11 RV 0h Reserved
10 RW 0b
INTxDisable: Interrupt Disable
This bit controls the ability of the PCI Express port to generate INTx messages.
This bit does not affect the ability of the processor to route interrupt messages
received at the PCI Express port. However, this bit controls the generation of
legacy interrupts to the DMI for PCI Express errors detected internally in this port
(for example, Malformed TLP, CRC error, completion time out, and so forth) or
when receiving RP error messages or interrupts due to HP/PM events generated in
legacy mode within the processor.
1 = Legacy Interrupt mode is disabled
0 = Legacy Interrupt mode is enabled
9RO0b
Fast Back-to-Back Enable
Not applicable to PCI Express must be hardwired to 0.
8RO0b
SERR Enable
For PCI Express/DMI ports, this field enables notifying the internal core error logic
of occurrence of an uncorrectable error (fatal or non-fatal) at the port. The
internal core error logic of IIO then decides if/how to escalate the error further
(pins/message, and so forth). This bit also controls the propagation of PCI Express
ERR_FATAL and ERR_NONFATAL messages received from the port to the internal
IIO core error logic.
1 = Fatal and Non-fatal error generation and Fatal and Non-fatal error message
forwarding is enabled
0 = Fatal and Non-fatal error generation and Fatal and Non-fatal error message
forwarding is disabled
Refer to PCI Express Base Specification, Revision 3.0 for details of how this bit is
used in conjunction with other control bits in the Root Control register for
forwarding errors detected on the PCI Express interface to the system core error
logic.
7RO0b
IDSEL Stepping/Wait Cycle Control
Not applicable to PCI Express must be hardwired to 0.
6RW0b
Parity Error Response
For PCI Express/DMI ports, IIO ignores this bit and always does ECC/parity
checking and signaling for data/address of transactions both to and from IIO. This
bit though affects the setting of bit 8 in the PCISTS register (see bit 8 in
Section 3.2.4.4, “PCISTS—PCI Status Register” ).
5RO0b
VGA palette snoop Enable
Not applicable to PCI Express; must be hardwired to 0.
4RO0b
Memory Write and Invalidate Enable
Not applicable to PCI Express; must be hardwired to 0.
3RO0b
Special Cycle Enable
Not applicable to PCI Express; must be hardwired to 0.
2RW0b
Bus Master Enable
1 = PCIe NTB will forward Memory Requests that it receives on its primary
internal interface to its secondary external link interface.
0 = PCIe NTB will not forward Memory Requests that it receives on its primary
internal interface. Memory requests received on the primary internal
interface will be returned to requester as an Unsupported Requests UR.
Requests other than Memory Requests are not controlled by this bit.
Reset Value value of this bit is 0b.