Datasheet

Processor Uncore Configuration Registers
472 Datasheet, Volume 2
4.4 Power Control Unit (PCU) Registers
4.4.1 CSR Register Maps
The following register maps are for Power Control Unit registers
Table 4-20. PCU0 Register Map: Device: 10 Function: 000h–104h
DID VID 0h 80h
PCISTS PCICMD 4h
PACKAGE_POWER_SKU
84h
CCR RID 8h 88h
BIST HDR PLAT CLSR Ch PACKAGE_POWER_SKU_UNIT 8Ch
10h PACKAGE_ENERGY_STATUS 90h
14h 94h
18h 98h
1Ch 9Ch
20h
PLATFORM_ID
A0h
24h A4h
28h
PLATFORM_INFO
A8h
SDID SVID 2Ch ACh
30h B0h
CAPPTR 34h PP0_Any_Thread_Activity B4h
38h PP0_Efficient_Cycles B8h
MAXLAT MINGNT INTPIN INTL 3Ch PP0_Thread_Activity BCh
40h C0h
44h C4h
48h Package_Temperature C8h
MEM_TRML_ESTIMATION_CONFIG 4Ch PP0_temperature CCh
MEM_TRML_ESTIMATION_CONFIG2 50h
D0h
54h PCU_REFERENCE_CLOCK D4h
58h P_STATE_LIMITS D8h
5Ch DCh
MEM_TRML_TEMPERATURE_REPORT 60h
E0h
MEM_ACCUMULATED_BW_CH_0 64h TEMPERATURE_TARGET E4h
MEM_ACCUMULATED_BW_CH_1 68h
TURBO_POWER_LIMIT
E8h
MEM_ACCUMULATED_BW_CH_2 6Ch ECh
MEM_ACCUMULATED_BW_CH_3 70h PRIP_TURBO_PWR_LIM F0h
74h F4h
78h
PRIMARY_PLANE_CURRENT_CONFIG_CONTROL
F8h
PRIP_NRG_STTS 7Ch FCh
DID VID 0h
80h