Datasheet

Processor Uncore Configuration Registers
468 Datasheet, Volume 2
16 RW 0b
Shared Credit Release
When set, prevents schedulers from speculatively allocating shared credits in the
local credit counter. This causes the idle state of the local credit counter to be
zero.
When cleared, shared credits are pre-allocated to both schedulers’ local counters,
allowing lower latency.
1 = Do not schedule from speculative allocating shared credit at local credit
counter;
0 = Allows speculative pre-allocate the local credit counters from shared credit
counter to reduce the latency
15 RW-V 0b
Scheduler 1 read enable
When set, read the credit counters from scheduler 1 and place the values in Main
Counter and Performance. Then the register resets this bit to 0. This ensures the
credit counter at the deterministic value at idle state for certain transitions.
1 = Read credit counters from scheduler 1
0 = Do not read credit from the scheduler 1. A 0 is default value at reset and
immediately follows reading out all credits (or after its was set).
14 RW-V 0b
Scheduler 0 read enable
When set, read the credit counters from scheduler 0 and place the values in Main
Counter and Performance. Then the register resets this bit to 0. This is insures the
credit counter at the deterministic value at idle state for certain transition.
1 = Read credit counters from scheduler 1
0 = Do not read credit from the scheduler 1. A 0 is default value at the reset and
immediately follows reading out all credits (or after its was set)
13 RW-V 0b
Write Enable
When set, write the credit counters in the both schedulers using the value from
Main Count. Software must ensure that credits are in idle state (all credit
returned) when writing the credit count. For shared credits, only the global count
is written. Software must ensure that Local Credit counter is zero when doing the
write by setting sharedCrditRls prior to doing the write.
1 = Write to schedulers by using main credit count value
0 = Do not write to scheduler counts
HaCrdtCnt
Bus: 1 Device: 14 Function: 0 Offset: 70h
Bit Attr
Reset
Value
Description