Datasheet

Processor Uncore Configuration Registers
466 Datasheet, Volume 2
4.3.2 Processor Home Agent Register
The Home agent is responsible for memory transactions and interacts with the
processor’s ring and handles incoming and outgoing transactions.
4.3.2.1 TMBAR—Thermal Memory Mapped Register Range Base
This is the base address for the Thermal Controller Memory Mapped space. There is no
physical memory within this 32 KB window that can be addressed. The 32 KB reserved
by this register does not alias to any PCI 2.2 compliant memory mapped space.
All TMBAR space maps the access to this memory space towards MCHBAR space. For
details of this BAR, refer to the MCHBAR specifications.
4.3.2.2 TAD[0:11]—Target Address Decode DRAM Rule Register
TMBAR
Bus: 1 Device: 14 Function: 0 Offset: 10h
Bit Attr
Reset
Value
Description
63:39 RV 0h Reserved
38:15 RO 000000
h
Thermal Memory Map Base Address
This field corresponds to bits 31:15 of the base address TMBAR address space.
BIOS programs this register resulting in a base address for a 32 KB block of
contiguous memory address space. This register ensures that a naturally aligned
32 KB space is allocated within total addressable memory space.
14:0 RV 0h Reserved
TAD[0:11]
Bus: 1 Device: 14 Function: 0 Offset: 40h, 44h, 48h, 4Ch, 50h, 54h, 58h,
5Ch
Bus: 1 Device: 14 Function: 0 Offset: 60h, 64h, 68h, 6Ch
Bit Attr
Reset
Value
Description
31:12 RWS-LB 00000h
TAD Limit
This field defines the memory region limit. It contains the physical address bit
range [45:26].
0 physical address [45:26] TAD[0].Limt , when N=0
TAD[N-1].limit+1 physical address [45:26] TAD[N].Limit; when N=1 to 11
Note: ì-LBî means uBox message ConfigRegWr can write to this register. However
ComfigWrLtLock can not write to this register.
11:10 RWS-LB 00b
Number of Socket Ways
This field defines the number of sockets interleave in the system.
00 = 1 way
01 = 2 ways
10 = 4 ways
11 = 8 ways
Reset Value value: 0 = 1 socket in the system