Datasheet

Processor Uncore Configuration Registers
464 Datasheet, Volume 2
4.2.16.36 x4modesel—MDCP X4 Mode Select Register
x4modesel
Bus: 1 Device: 16 Function: 2 Offset: 268h
Bus: 1 Device: 16 Function: 3 Offset: 268h
Bus: 1 Device: 16 Function: 6 Offset: 268h
Bus: 1 Device: 16 Function: 7 Offset: 268h
Bit Attr
Reset
Value
Description
31:3 RV 0h Reserved
2RW0b
DIMM2_MODE
Controls the DDRIO x4 (if set) / x8 (if cleared) DIMM2 DQS select.
1RW0b
DIMM1_MODE
Controls the DDRIO x4 (if set) / x8 (if cleared) DIMM1 DQS select.
0RW0b
DIMM0_MODE
Controls the DDRIO x4 (if set) / x8 (if cleared) DIMM0 DQS select.