Datasheet
Processor Integrated I/O (IIO) Configuration Registers
46 Datasheet, Volume 2
Table 3-7. Device 0/Function 0 DMI2 mode), Devices 2/Functions 0 (PCIe* Root Port),ï€
and Device 3/Function 0 (PCIe* Root Port) Extended Configuration Map –ï€
Offset 400h–4FCh
400h XPPMDL0 480h
404h XPPMDL1 484h
408h XPPMCL0 488h
40Ch XPPMCL1 48Ch
410h XPPMCH XPPMDH 490h
414h XPPMR0 494h
418h XPPMR1 498h
41Ch XPPMEVL0 49Ch
420h XPPMEVL1 4A0h
424h XPPMEVH0 4A4h
428h XPPMEVH1 4A8h
42Ch XPPMER0 4ACh
430h XPPMER1 4B0h
434h
4B4h
438h 4B8h
43Ch 4BCh
440h 4C0h
444h 4C4h
448h 4C8h
44Ch 4CCh
450h 4D0h
454h 4D4h
458h 4D8h
45Ch 4DCh
460h 4E0h
464h 4E4h
468h 4E8h
46Ch 4ECh
470h 4F0h
474h 4F4h
478h 4F8h
47Ch 4FCh