Datasheet

Datasheet, Volume 2 459
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Processor Uncore Configuration Registers
4.2.16.27 IOSAV_DQ_LFSR1 Register
4.2.16.28 IOSAV_DQ_LFSRSEED1 Register
IOSAV_DQ_LFSR1
Bus: 1 Device: 16 Function: 2 Offset: 1C8h
Bus: 1 Device: 16 Function: 6 Offset: 1C8h
Bus: 1 Device: 16 Function: 3 Offset: 1C8h
Bus: 1 Device: 16 Function: 7 Offset: 1C8h
Bit Attr
Reset
Value
Description
31:27 RW 0h
NUMBITS
Number of bits in the LFSR – maximum is 29 decimal.
26:0 RW
000000
0h
FBVEC
LFSR XOR feedback tap points mask position.LFSR Example:
MTLFSR.NUMBITS = 0x5 5 flop lsfr, with feedback taken lfsr[4] output
MTLFSR.FBVEC = 0x9 Feedback tap points at X^3 and X^0
Generating function: G(X) = X^5 + X^3 + 1
Physical implementation
----------------------------------------------------------
| -----------------------------------------------
| | ------------------------------
| | | ------------------ NOR --
| | | | ------- |
| | | | | |
-- Lfsr[4] -- Lfsr[3] - XOR - Lfsr[2] -- Lfsr[1] -- Lfsr[0] - XOR
| | |
-----------------------------------------------------------------
IOSAV_DQ_LFSRSEED1
Bus: 1 Device: 16 Function: 2 Offset: 1CCh
Bus: 1 Device: 16 Function: 6 Offset: 1CCh
Bus: 1 Device: 16 Function: 3 Offset: 1CCh
Bus: 1 Device: 16 Function: 7 Offset: 1CCh
Bit Attr
Reset
Value
Description
31:27 RV 0h Reserved
26:0 RW 0h
SEED
Start value for LFSR address sequence.