Datasheet

Processor Uncore Configuration Registers
456 Datasheet, Volume 2
4.2.16.21 IOSAV_CH_B8_BW_SERR Register
When an error occurs on one of the data pins, the corresponding bit in this register is
set. Bits may be cleared by implicit write. At the end of a sequence (or few sequences
ran one after the other without clearing the register), every bit that was set means that
there was at least one error in the corresponding bit in the sequence. Every clear bit
means that there were no errors in the whole sequence
4.2.16.22 IOSAV_CH_B0_B3_BW_MASK Register
IOSAV bit-wise compare mask registers – Each bit, if set, blocks the corresponding
data bit compare.
IOSAV_CH_B8_BW_SERR
Bus: 1 Device: 16 Function: 2 Offset: 1A8h
Bus: 1 Device: 16 Function: 6 Offset: 1A8h
Bus: 1 Device: 16 Function: 3 Offset: 1A8h
Bus: 1 Device: 16 Function: 7 Offset: 1A8h
Bit Attr
Reset
Value
Description
31:8 RV 0h Reserved
7:0 RW1CS 00h
B8_BW_SERROR
Bit-wise error
IOSAV_CH_B0_B3_BW_MASK
Bus: 1 Device: 16 Function: 2 Offset: 1B0h
Bus: 1 Device: 16 Function: 6 Offset: 1A8h
Bus: 1 Device: 16 Function: 3 Offset: 1B0h
Bus: 1 Device: 16 Function: 7 Offset: 1A8h
Bit Attr
Reset
Value
Description
31:24
See
Description
See
Description
B3_BW_MASK
Bit-wise compare mask
1_16_2_CFG: Attr: RWS Reset Value: FFh
1_16_6_CFG: Attr: RV Reset Value: 0h
23:16
See
Description
See
Description
B2_BW_MASK
Bit-wise compare mask
1_16_2_CFG: Attr: RWS Reset Value: FFh
1_16_6_CFG: Attr: RW1CS Reset Value: 00h
15:8 RWS FFh
B1_BW_MASK
Bit-wise compare mask
7:0 RWS FFh
B0_BW_MASK
Bit-wise compare mask