Datasheet

Datasheet, Volume 2 455
Processor Uncore Configuration Registers
4.2.16.19 IOSAV_CH_B0_B3_BW_SERR Register
When an error occurs on one of the data pins, the corresponding bit in this register is
set. Bits may be cleared by implicit write. At the end of a sequence (or few sequences
ran one after the other without clearing the register), every bit that was set means that
there was at least one error in the corresponding bit in the sequence. Every clear bit
means that there were no errors in the whole sequence
4.2.16.20 IOSAV_CH_B4_B7_BW_SERR Register
When an error occurs on one of the data pins, the corresponding bit in this register is
set. Bits may be cleared by implicit write. At the end of a sequence (or few sequences
ran one after the other without clearing the register), every bit that was set means that
there was at least one error in the corresponding bit in the sequence. Every clear bit
means that there were no errors in the whole sequence
IOSAV_CH_B0_B3_BW_SERR
Bus: 1 Device: 16 Function: 2 Offset: 1A0h
Bus: 1 Device: 16 Function: 3 Offset: 1A0h
Bus: 1 Device: 16 Function: 6 Offset: 1A0h
Bus: 1 Device: 16 Function: 7 Offset: 1A0h
Bit Attr
Reset
Value
Description
31:24 RW1CS 00h
B3_BW_SERROR
Bit-wise error
23:16 RW1CS 00h
B2_BW_SERROR
Bit-wise error
15:8 RW1CS 00h
B1_BW_SERROR
Bit-wise error
7:0 RW1CS 00h
B0_BW_SERROR
Bit-wise error
IOSAV_CH_B4_B7_BW_SERR
Bus: 1 Device: 16 Function: 2 Offset: 1A4h
Bus: 1 Device: 16 Function: 6 Offset: 1A4h
Bus: 1 Device: 16 Function: 3 Offset: 1A4h
Bus: 1 Device: 16 Function: 7 Offset: 1A4h
Bit Attr
Reset
Value
Description
31:24 RW1CS 00h
B7_BW_SERROR
Bit-wise error
23:16 RW1CS 00h
B6_BW_SERROR
Bit-wise error
15:8 RW1CS 00h
B5_BW_SERROR
Bit-wise error
7:0 RW1CS 00h
B4_BW_SERROR
Bit-wise error