Datasheet

Datasheet, Volume 2 453
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Processor Uncore Configuration Registers
4.2.16.17 LEAKY_BKT_2ND_CNTR_REG Register
LEAKY_BKT_2ND_CNTR_REG
Bus: 1 Device: 16 Function: 2 Offset: 138h
Bus: 1 Device: 16 Function: 6 Offset: 138h
Bit Attr
Reset
Value
Description
31:16 RW 0000h
LEAKY_BKT_2ND_CNTR_LIMIT
Secondary Leaky Bucket Counter Limit (2b per DIMM). This register defines the
secondary leaky bucket counter limit for all 8 logical ranks within channel. The
counter logic will generate the secondary LEAK pulse to decrement the rank’s
correctable error counter by 1 when the corresponding rank leaky bucket rank
counter roll over at the predefined counter limit. The counter increment at the
primary leak pulse from the LEAKY_BUCKET_CNTR_LO and
LEAKY_BUCKET_CNTR_HI logic.
Bit[31:30] = Rank 7 Secondary Leaky Bucket Counter Limit
Bit[29:28] = Rank 6 Secondary Leaky Bucket Counter Limit
Bit[27:26] = Rank 5 Secondary Leaky Bucket Counter Limit
Bit[25:24] = Rank 4 Secondary Leaky Bucket Counter Limit
Bit[23:22] = Rank 3 Secondary Leaky Bucket Counter Limit
Bit[21:20] = Rank 2 Secondary Leaky Bucket Counter Limit
Bit[19:18] = Rank 1 Secondary Leaky Bucket Counter Limit
Bit[17:16] = Rank 0 Secondary Leaky Bucket Counter Limit
0h = LEAK pulse is generated one DCLK after the counter roll over at 3.
1h = LEAK pulse is generated one DCLK after the primary LEAK pulse is asserted.
2h = LEAK pulse is generated one DCLK after the counter roll over at 1.
3h = LEAK pulse is generated one DCLK after the counter roll over at 2.
15:0 RW-V 0000h
LEAKY_BKT_2ND_CNTR
Per rank secondary leaky bucket counter (2b per rank)
bit 15:14 = Rank 7 secondary leaky bucket counter
bit 13:12 = Rank 6 secondary leaky bucket counter
bit 11:10 = Rank 5 secondary leaky bucket counter
bit 9:8 = Rank 4 secondary leaky bucket counter
bit 7:6 = Rank 3 secondary leaky bucket counter
bit 5:4 = Rank 2 secondary leaky bucket counter
bit 3:2 = Rank 1 secondary leaky bucket counter
bit 1:0 = Rank 0 secondary leaky bucket counter