Datasheet

Datasheet, Volume 2 45

Processor Integrated I/O (IIO) Configuration Registers
Note:
1. Applicable to Device 0,2,3/Function 0.
2. Applicable to Device 2/Function 0.
3. Applicable to Device 2,3/Function 0.
4. Applicable to Device 1-3.
5. Applicable to Device 1/Function 0 and Device 2,3/Function 0,2.
Table 3-6. Device 1/Functions 0-1 (PCIe* Root Ports), Devices 2/Functions 0–3 
(PCIe* Root Ports), and Device 3/Function 0–3 (PCIe* Root Ports)
Extended Configuration Map – Offset 200h–2FCh
XPCORERRSTS 200h LER_CAP 280h
XPCORERRMSK 204h LER_HDR 284h
XPUNCERRSTS 208h LER_CTRLSTS 288h
XPUNCERRMSK 20Ch LER_UNCERRMSK 28Ch
XPUNCERRSEV 210h LER_XPUNCERRMSK 290h
XPUNCERR
PTR
214h
LER_RPERRMSK
294h
UNCEDMASK 218h
298h
COREDMASK 21Ch
29Ch
RPEDMASK 220h
2A0h
XPUNCEDMASK 224h
2A4h
XPCOREDMASK 228h
2A8h
22Ch 2ACh
XPGLBERRPTR XPGLBERRSTS 230h
2B0h
234h 2B4h
238h 2B8h
23Ch 2BCh
240h 2C0h
244h 2C4h
248h 2C8h
24Ch 2CCh
PXP2CAP
4
250h 2D0h
LNKCON3
4
254h 2D4h
LNERRSTS
4
258h 2D8h
LN1EQ
4
LN0EQ
4
25Ch 2DCh
LN3EQ
4
LN2EQ
4
260h 2E0h
LN5EQ
5
LN4EQ
5
264h 2E4h
LN7EQ
5
LN6EQ
5
268h 2E8h
LN9EQ
3
LN8EQ
3
26Ch 2ECh
LN11EQ
3
LN10EQ
3
270h XPPMDFXMAT0
1
2F0h
LN13EQ
3
LN12EQ
3
274h XPPMDFXMAT1
2
2F4h
LN15EQ
3
LN14EQ
3
278h XPPMDFXMSK0
3
2F8h
27Ch XPPMDFXMSK1
3
2FCh