Datasheet

Datasheet, Volume 2 447
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Processor Uncore Configuration Registers
4.2.16.7 WDBPRELOADCTRL—WDB Preload Control Register
The following is an example to program this register. If you want to load entry 0 with a
01010101... Pattern on each DQ bit, the registers would be programmed as follows:
• WDBPRELOADREG0[31:0] = 32’hFF00_FF00
• WDBPRELOADREG1[31:0] = 32’hFF00_FF00
• WDBPRELOADCTRL[31:0] = 32’h8000_FFFF
To clear entry 31:
• WDBPRELOADREG0[31:0] = 32’h0000_0000
• WDBPRELOADREG1[31:0] = 32’h0000_0000
• WDBPRELOADCTRL[31:0] = 32’h801F_FFFF
If you want to load entry 31 such that only DQ0 will toggle with a 01010101.. Pattern:
• WDBPRELOADREG0[31:0] = 32’h0100_0100
• WDBPRELOADREG1[31:0] = 32’h0100_0100
• WDBPRELOADCTRL[31:0] = 32’h801F_0101
WDBPRELOADERCTRL
Bus: 1 Device: 16 Function: 2 Offset: A0h
Bus: 1 Device: 16 Function: 3 Offset: A0h
Bus: 1 Device: 16 Function: 6 Offset: A0h
Bus: 1 Device: 16 Function: 7 Offset: A0h
Bit Attr
Reset
Value
Description
31 RW-LBV 0b
STARTLOAD
Start to load data into WDB when set. Hardware will clear when load completes.
30:21 RV 0h Reserved
20:16 RW-LB 00h
WDB_ENTRY_NUM
WDB entry number to write data into.
15:8 RW-LB 00h
BYTEEN_2468XFER
Byte Enables for each byte of the DDR bus on 2nd, 4th, 6th and 8th transfers.
7:0 RW-LB 00h
BYTEEN_1357XFER
Byte Enables for each byte of the DDR bus on 1st, 3rd, 5th, and 7th transfers.