Datasheet

Processor Uncore Configuration Registers
446 Datasheet, Volume 2
4.2.16.5 WDBPRELOADREG0—WDB Data Load Register 0
4.2.16.6 WDBPRELOADREG1—WDB Data Load Register 1
WDB Data Load Register 0
Bus: 1 Device: 16 Function: 2 Offset: 98h
Bus: 1 Device: 16 Function: 3 Offset: 98h
Bus: 1 Device: 16 Function: 6 Offset: 98h
Bus: 1 Device: 16 Function: 7 Offset: 98h
Bit Attr
Reset
Value
Description
31:24 RW-LB 00h XFER4
4th transfer on a byte of the DDR Bus.
23:16 RW-LB 00h XFER3
3rd transfer on a byte of the DDR Bus.
15:8 RW-LB 00h XFER2
2nd transfer on a byte of the DDR Bus.
7:0 RW-LB 00h XFER1
1st transfer on a byte of the DDR Bus.
WDBPRELOADREG1
Bus: 1 Device: 16 Function: 2 Offset: 9Ch
Bus: 1 Device: 16 Function: 3 Offset: 9Ch
Bus: 1 Device: 16 Function: 6 Offset: 9Ch
Bus: 1 Device: 16 Function: 7 Offset: 9Ch
Bit Attr
Reset
Value
Description
31:24 RW-LB 00h
XFER8
8th transfer on a byte of the DDR Bus.
23:16 RW-LB 00h
XFER7
7th transfer on a byte of the DDR Bus.
15:8 RW-LB 00h
XFER6
6th transfer on a byte of the DDR Bus.
7:0 RW-LB 00h
XFER5
5th transfer on a byte of the DDR Bus.