Datasheet

Processor Uncore Configuration Registers
442 Datasheet, Volume 2
4.2.15.7 IOSAV_CH_STAT—IOSAV Channel Status Register
This register is cleared when writing to the REPEAT field of IOSAV_CH_SEQ_CTRL.
IOSAV_CH_STAT
Bus: 1 Device: 16 Function: 0 Offset: 454h
Bus: 1 Device: 16 Function: 1 Offset: 454h
Bus: 1 Device: 16 Function: 4 Offset: 454h
Bus: 1 Device: 16 Function: 5 Offset: 454h
Bit Attr
Reset
Value
Description
31:8 RV 0h Reserved
7RO-V0b
DONE_AND_REF_DRAINED
This bit is cleared with the Idle-done bit when a new sequence is written. It is set
when the sequence is completed and the refresh counter is drained. For example,
if during the sequence the T_REFI counter has accumulated to 6, then this bit
remains clear until 6 refreshes have been executed after sequence (assuming no
additional T_REFI increment has occurred during this time).
6RO-V0bRCOMP failure
5RV0hReserved
4RO-V0b
REF_FAILURE
This bit is set when a sequence was stopped by a panic refresh, and cleared when
a new sequence is loaded (repeat is rewritten).
3RO-V0b
STOP_ERROR
This bit is set when a sequence was stopped by error, and cleared when a new
sequence is loaded (repeat is rewritten).
2RO-V0b
IDLE_DONE
This bit is set when execution is completed and cleared when a new sequence is
loaded (repeat is rewritten).
1RO-V0b
RUN
This bit is set when execution of the sequence begins and cleared when execution
ends.
0RO-V0b
IDLE_READY
This bit is set when a sequence is programmed (Repeat counter is non-zero) but
sequence execution did not start because start conditions are not fulfilled. It is
cleared when run has begun.