Datasheet

Processor Uncore Configuration Registers
440 Datasheet, Volume 2
4.2.15.5 IOSAV_CH_SUBSEQ_CTRL_[0:3]—IOSAV Channel Sub-Sequence 
Control Seq 0 Register
The RW-L field is locked by either NORMAL bit in MCMTR register or by IOSAV_DISABLE
bit in LT_IOSAV_MEMINIT_DIS register.
9:4 RW-L 0h
CKE: Clock Enables
CKE[5] = D2 CKE1
CKE[4] = D2 CKE0
CKE[3] = D1 CKE1
CKE[2] = D1 CKE0
CKE[1] = D0 CKE1
CKE[0] = D0 CKE0
3RV0hReserved
2RW-L 1b
WE_NN: WE# Control
A value zero means asserted.
1RW-L 1b
CAS_NN: CAS# Control
A value zero means asserted.
0RW-L 1b
RAS_NN: RAS# Control
Avalue zero means asserted.
IOSAV_CH_SPCL_CMD_CTRL_[0:3]
Bus: 1 Device: 16 Function: 0 Offset: 430h, 434h, 438h, 43Ch
Bus: 1 Device: 16 Function: 1 Offset: 430h, 434h, 438h, 43Ch
Bus: 1 Device: 16 Function: 4 Offset: 430h, 434h, 438h, 43Ch
Bus: 1 Device: 16 Function: 5 Offset: 430h, 434h, 438h, 43Ch
Bit Attr
Reset
Value
Description
IOSAV_CH_SUBSEQ_CTRL_[0:3]
Bus: 1 Device: 16 Function: 0 Offset: 440h, 444h, 448h, 44Ch
Bus: 1 Device: 16 Function: 1 Offset: 440h, 444h, 448h, 44Ch
Bus: 1 Device: 16 Function: 4 Offset: 440h, 444h, 448h, 44Ch
Bus: 1 Device: 16 Function: 5 Offset: 440h, 444h, 448h, 44Ch
Bit Attr
Reset
Value
Description
31:22 RV 0h Reserved
21:20 RW-L 00b
DIR
00 = Non-data command
01 = RD
10 = WR
11 = RD&WR
19:16 RW-L 4h
GAP
This field defines the number of DCLK cycles (GAP+1) between issuing commands
within the sub-sequence (minimum setting GAP=3 for minimum actual gap time
of 4).
15:8 RW-L 04h
WAIT
This field defines the number of DCLK cycles (WAIT+1) between completion of this
sub-sequence and beginning the next sub-sequence (minimum setting WAIT=3
for minimum wait time of 4).
7:0 RW-L 00h
REPEAT
How many times this command is repeated in single execution of the sub-
sequence. The value FFh stands for infinity.