Datasheet

Datasheet, Volume 2 439

Processor Uncore Configuration Registers
4.2.15.3 IOSAV_CH_ADDR_LFSR_[0:3]— IOSAV Channel Address 
LFSR Seq 0 Register
The RW-L field is locked by either NORMAL bit in MCMTR register or by IOSAV_DISABLE
bit in LT_IOSAV_MEMINIT_DIS register.
4.2.15.4 IOSAV_CH_SPCL_CMD_CTRL_[0:3]—IOSAV Channel Special
Command Control Seq 0 Register
The RW-L field is locked by either NORMAL bit in MCMTR register or by IOSAV_DISABLE
bit in LT_IOSAV_MEMINIT_DIS register.
IOSAV_CH_ADDR_LFSR_[0:3]
Bus: 1 Device: 16 Function: 0 Offset: 420h, 424h, 428h, 42Ch
Bus: 1 Device: 16 Function: 1 Offset: 420h, 424h, 428h, 42Ch
Bus: 1 Device: 16 Function: 4 Offset: 420h, 424h, 428h, 42Ch
Bus: 1 Device: 16 Function: 5 Offset: 420h, 424h, 428h, 42Ch
Bit Attr
Reset
Value
Description
31:24 RV 0h Reserved
23:0 RW-L 000000h
LFSR: 23-bit LFSR Field
This keeps the LFSR current value of the sequence. It is written into the LFSR
when sub-sequence is loaded and loaded from LFSR when the sub-sequence is
done.
IOSAV_CH_SPCL_CMD_CTRL_[0:3]
Bus: 1 Device: 16 Function: 0 Offset: 430h, 434h, 438h, 43Ch
Bus: 1 Device: 16 Function: 1 Offset: 430h, 434h, 438h, 43Ch
Bus: 1 Device: 16 Function: 4 Offset: 430h, 434h, 438h, 43Ch
Bus: 1 Device: 16 Function: 5 Offset: 430h, 434h, 438h, 43Ch
Bit Attr
Reset
Value
Description
31:30 RV 0h Reserved
29 RW-L 0b
AP
Auto PrechargeAddress bit 10 as Auto Precharged (when 10 address bits are
relevant)
28:18 RW-L 000h
CS_CTL
Control the CS signal
00XX_XXXX_XXXX: all CS’ are X
01XX_XXXX_XXXX: !((decode of IOSAV_ch#_<ssq>_special_command_ADDR
Rank (CS) field) | !X (bitwise OR)
Example: CS_ctl == 0x403, and IOSAV_ch#_<ssq>_special_command_ADDR
Rank (CS) ==1h, CS pins shall be 2h (bits 0, 2 & 3 are asserted, bit 1 is de-
asserted, all active low)
17:10 RW-L 00h
ODT: On Die Termination
ODT[7] = reserved for future use
ODT[6] = reserved for future use
ODT[5] = D2 ODT1
ODT[4] = D2 ODT0
ODT[3] = D1 ODT1
ODT[2] = D1 ODT0
ODT[1] = D0 ODT1
ODT[0] = D0 ODT0