Datasheet

Processor Uncore Configuration Registers
438 Datasheet, Volume 2
4.2.15.2 IOSAV_CH_ADDR_UPDT_[0:3]—IOSAV Channel Address 
Update Seq 0 Register
Need to accommodate slot increment
The RW-L field is locked by either NORMAL bit in MCMTR register or by IOSAV_DISABLE
bit in LT_IOSAV_MEMINIT_DIS register.
IOSAV_CH_ADDR_UPDT_[0:3]
Bus: 1 Device: 16 Function: 0 Offset: 410h, 414h, 418h, 41Ch
Bus: 1 Device: 16 Function: 1 Offset: 410h, 414h, 418h, 41Ch
Bus: 1 Device: 16 Function: 4 Offset: 410h, 414h, 418h, 41Ch
Bus: 1 Device: 16 Function: 5 Offset: 410h, 414h, 418h, 41Ch
Bit Attr
Reset
Value
Description
31:18 RV 0h Reserved
17:16 RW-L 00b
Deselect Cycles Control
This field defines the behavior of LFSR on the deselect cycles (cycles in which no
sub-seq command is issued)
0h = No change – last issued command is driven with no change
1h = LFSR is XORing with address & command (not including CS), but not
updating
2h = LFSR is XORing with address & command (not including CS), and updating
15:12 RW-L 0h
UPDT_RATE
This field defines once every how many command issues the address is updated.
The programmed value should be the (required-rate – 1). For example, in order to
get an update every second command issue, the programmed value should be 1.
If the programmed value is zero, address is updated every command issue.
11:10 RW-L 00b
LFSR_UPDT: LFSR Update
This field defines the LFSR function as following
00 = No LFSR function
10 = LFSR function on bits [Address wrap : 0]
11 = LFSR function on bits [Address wrap : 3]
9:5 RW-L 0h
ADR_WRAP_LFSR_MSK
This field defines the bit range of the address may be updated. Bit range is
[(Address wrap) : 0]
4:0 RW-L 0h
ADR_INC: Address Increment
The address field is incremented by this field every time there is an address
update.
Bit 0 = Increment RAS / CAS address by 1
Bit 1 = Increment RAS / CAS address by 8
Bit 2 = Increment bank select by 1
Bits 4:3 = Increment rank select by 1, 2 or 3 (two bits)
Except for bits 0 & 1, any bit combination may be applied. For example, by
setting bits 0 and 2, the address and bank select are incremented every time the
address is updated
Note: The address that is incremented is the concatenation of rank # (encoded),
bank # and row/column relevant address bits. Example
Rank (CS) = 0b0010 (rank #1 is selected)
Bank = 0b101 (bank 5)
# of row bits = 14
Row address = 2BCDh == 0b 10 1011 1100 1101
This case address is 0b 01 101 10101111001101 (rank, bank row) == 36BCDh