Datasheet

Datasheet, Volume 2 437
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Processor Uncore Configuration Registers
4.2.14.28 SPARING Register
This is the Sparing Credit register
4.2.15 Integrated Memory Controller DDR3 Training Registers
4.2.15.1 IOSAV_SPEC_CMD_ADDR_[0:3]—IOSAV Special Command 
ADDR Seq 0 Register
The RW-L field is locked by either NORMAL bit in MCMTR register or by IOSAV_DISABLE
bit in LT_IOSAV_MEMINIT_DIS register.
SPARING
Bus: 1 Device: 16 Function: 0 Offset: 338h
Bus: 1 Device: 16 Function: 1 Offset: 338h
Bus: 1 Device: 16 Function: 4 Offset: 338h
Bus: 1 Device: 16 Function: 5 Offset: 338h
Bit Attr
Reset
Value
Description
31:14 RV 0h Reserved
13:8 RW 05h
WRFIFOHWM
This field provides the maximum number of merged write isoch transactions
allowed in a channel. When this level is exceeded, write credits will not be
returned. A value of 0 disables this feature and allows any number of merged
write isoch transactions, which can lead to unexpected behavior.
7:6 RV 0h Reserved
5:0 RW 00h
SpareCrdts
This field provides the number of WPQ credits to withhold from HA while sparing is
in progress.
IOSAV_SPEC_CMD_ADDR_[0:3]
Bus: 1 Device: 16 Function: 0 Offset: 400h, 404h, 408h, 40Ch
Bus: 1 Device: 16 Function: 1 Offset: 400h, 404h, 408h, 40Ch
Bus: 1 Device: 16 Function: 4 Offset: 400h, 404h, 408h, 40Ch
Bus: 1 Device: 16 Function: 5 Offset: 400h, 404h, 408h, 40Ch
Bit Attr
Reset
Value
Description
31:28 RV 0h Reserved
27:24 RW-L 0h
TGT_RANK
Physical Rank CS Select at the target DIMM Slot; that is, CS[9:0]#.
23:21 RW-L 000b Bank: Bank Address
20:18 RW-L 000b
ROW_ADR_WIDTH
For different DDR chip size, this field defines how many ADDR bits are relevant:
0h = 10 bits (9:0) - Only in this mode AP bit in
IOSAV_ch#_<ssq>_special_command_CTL is valid
1h = 18 bits (17:0) (reserved for HDRL-2)
2h = 12 bits (11:0)
3h = 13 bits (12:0)
4h = 14 bits (13:0)
5h = 15 bits (14:0)
6h = 16 bits (15:0)
7h = 17 bits (16:0) (reserved for HDRL-2)
17:0 RW-L 00000h ROW_COL_ADR: Row Column Address