Datasheet

Datasheet, Volume 2 435
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Processor Uncore Configuration Registers
4.2.14.24 RSP_FUNC_MCCTRL_ERR_INJ Register
Error Injection Response Function
This register is locked by EPMCMAIN_DFX_LCK_CNTL.RSPLCK (uCR) AND
MC_ERR_INJ_LCK.MC_ERR_INJ_LCK (MSR).
The referenced Used Trigger-0/Use Trigger-1/Use Trigger-2 are being mapped as the
followings:
• 01 - Use Trigger-0 from MCGLBRSPCNTL.GlbRsp0
• 10 - Use Trigger-1 from MCGLBRSPCNTL.GlbRsp1
• 11 - Use Trigger-2 from MCGLBRSPCNTL.GlbRsp2
4.2.14.25 PWMM_STARV_CNTR_PRESCALER Register
This register is the Partial Write Starvation Counter Pre-scaler
RSP_FUNC_MCCTRL_ERR_INJ
Bus: 1 Device: 16 Function: 0 Offset: 300h
Bus: 1 Device: 16 Function: 1 Offset: 300h
Bus: 1 Device: 16 Function: 4 Offset: 300h
Bus: 1 Device: 16 Function: 5 Offset: 300h
Bit Attr
Reset
Value
Description
31:16 RV 0h Reserved
15:14 RWS-L 00b
RD_RETRY_INJ_SEL
Read Retry Error Injection Selection:
00 = Do not Inject,
01 = Use Trigger-0,
10 = Use Trigger-1,
11 = Use Trigger-2
7:4 RV 0h Reserved
PWMM_STARV_CNTR_PRESCALER
Bus: 1 Device: 16 Function: 0 Offset: 304h
Bus: 1 Device: 16 Function: 1 Offset: 304h
Bus: 1 Device: 16 Function: 4 Offset: 304h
Bus: 1 Device: 16 Function: 5 Offset: 304h
Bit Attr
Reset
Value
Description
31 RW 0b
dis_wim_exit_block
Disable scheduler blocking when exiting write isoch mode
30 RW 0b
wmm_exit_in_wim
Allow write major mode exit while in write isoch mode
29:24 RW 1Dh
WPQ Isoch WM
When WDB level reaches this WM, the MC is in Isoch mode.
Value must be greater than WMM_ENTER and between (RPQ size + 5) and 29.