Datasheet

Processor Uncore Configuration Registers
434 Datasheet, Volume 2
4.2.14.22 WR_ODT_TBL2—Write ODT Lookup Table 2 Register
One entry for each physical rank on each channel. Each entry defines which ODT
signals are asserted when accessing that rank. This register also includes ODT timing
control.
The recommended BIOS settings to keep the MC_TERM_RNK_MSK consistent are:
• Set Write ODT mapping – write ODT specified all ODT pins assertion for a write
targeting at this rank. All DIMM's termination rank must have the ODT mask
asserted. All non-termination rank in the ODT mapping table must be cleared
4.2.14.23 MC_INIT_STAT_C Register
State register per channel. Sets control signals static values. Power-up default is state
0h set by global reset.
BIOS should leave this register default to zero since the processor has Read/Write ODT
table logic to control ODT dynamically during IOSAV or NORMAL modes.
WR_ODT_TBL2
Bus: 1 Device: 16 Function: 0 Offset: 278h
Bus: 1 Device: 16 Function: 1 Offset: 278h
Bus: 1 Device: 16 Function: 4 Offset: 278h
Bus: 1 Device: 16 Function: 5 Offset: 278h
Bit Attr
Reset
Value
Description
31:22 RV 0h Reserved
21:20 RW 00b
EXTRA_TRAILING_ODT
Extra Trailing ODT cycles
19:18 RV 0h Reserved
17:16 RW 00b
EXTRA_LEADING_ODT
Extra Leading ODT cycles
15:14 RV 0h Reserved
13:8 RW 0h
WR_ODT_RANK9
Rank 9 Write ODT
7:6 RV 0h Reserved
5:0 RW 0h
WR_ODT_RANK8
Rank 8 Write ODT
MC_INIT_STAT_C
Bus: 1 Device: 16 Function: 0 Offset: 280h
Bus: 1 Device: 16 Function: 1 Offset: 280h
Bus: 1 Device: 16 Function: 4 Offset: 280h
Bus: 1 Device: 16 Function: 5 Offset: 280h
Bit Attr
Reset
Value
Description
31:14 RV 0h Reserved
7:6 RV 0h Reserved
5:0 RW-L 0h
CKE ON OVERRIDE
1 = The bit overrides and asserts the corresponding CKE[5:0] output signal
during IOSAV mode.
0 = CKE pin is controlled by the IMC IOSAV logic.