Datasheet

Processor Uncore Configuration Registers
432 Datasheet, Volume 2
4.2.14.20 WR_ODT_TBL0—Write ODT Lookup Table 0 Register
One entry for each physical rank on each channel. Each entry defines which ODT
signals are asserted when accessing that rank. This register also includes ODT timing
control.
The recommended BIOS settings to keep the MC_TERM_RNK_MSK consistent are:
• Set Write ODT mapping - write ODT specified all ODT pins assertion for a write
targeting at this rank. All DIMM's termination rank must have the ODT mask
asserted. All non-termination rank in the ODT mapping table must be cleared.
WR_ODT_TBL0
Bus: 1 Device: 16 Function: 0 Offset: 270h
Bus: 1 Device: 16 Function: 1 Offset: 270h
Bus: 1 Device: 16 Function: 4 Offset: 270h
Bus: 1 Device: 16 Function: 5 Offset: 270h
Bit Attr
Reset
Value
Description
31:30 RV 0h Reserved
29:24 RW 0h
WR_ODT_RANK3
Rank 3 Write ODT
23:22 RV 0h Reserved
21:16 RW 0h
WR_ODT_RANK2
Rank 2 Write ODT
15:14 RV 0h Reserved
13:8 RW 0h
WR_ODT_RANK1
Rank 1 Write ODT
7:6 RV 0h Reserved
5:0 RW 0h
WR_ODT_RANK0
Rank 0 Write ODT