Datasheet

Processor Uncore Configuration Registers
430 Datasheet, Volume 2
4.2.14.18 RD_ODT_TBL1—Read ODT Lookup Table 1 Register
One entry for each physical rank on each channel. Each entry defines which ODT
signals are asserted when accessing that rank. This register also includes ODT timing
control.
The recommended BIOS settings to keep the MC_TERM_RNK_MSK consistent are:
• Set Read ODT mapping – read ODT specifies all ODT pins assertion for a read
targeting at this rank. Cear read target DIMM’s termination rank bit. The non-target
DIMM's termination rank bits must be set. All non-termination rank in the ODT
mapping table must be cleared.
13:8 RW 0h
RD_ODT_RANK1
Rank 1 Read ODT pins
7:6 RV 0h Reserved
5:0 RW 0h
RD_ODT_RANK0
Rank 0 Read ODT pins
RD_ODT_TBL0
Bus: 1 Device: 16 Function: 0 Offset: 260h
Bus: 1 Device: 16 Function: 1 Offset: 260h
Bus: 1 Device: 16 Function: 4 Offset: 260h
Bus: 1 Device: 16 Function: 5 Offset: 260h
Bit Attr
Reset
Value
Description
RD_ODT_TBL1
Bus: 1 Device: 16 Function: 0 Offset: 264h
Bus: 1 Device: 16 Function: 1 Offset: 264h
Bus: 1 Device: 16 Function: 4 Offset: 264h
Bus: 1 Device: 16 Function: 5 Offset: 264h
Bit Attr
Reset
Value
Description
31:30 RV 0h Reserved
29:24 RW 0h
RD_ODT_RANK7
Rank 7 Read ODT pins
23:22 RV 0h Reserved
21:16 RW 0h
RD_ODT_RANK6
Rank 6 Read ODT pins
15:14 RV 0h Reserved
13:8 RW 0h
RD_ODT_RANK5
Rank 5 Read ODT pins
7:6 RV 0h Reserved
5:0 RW 0h
RD_ODT_RANK4
Rank 4 Read ODT pins