Datasheet

Datasheet, Volume 2 43

Processor Integrated I/O (IIO) Configuration Registers
Table 3-4. Device 1/Functions 0-1 (PCIe* Root Ports), Devices 2/Functions 0–3 
(PCIe* Root Ports), and Device 3/Function 0–3 (PCIe* Root Ports) 
Legacy Configuration Map
DID VID 0h 80h
PCISTS PCICMD 4h 84h
CCR RID 8h 88h
BIST HDR PLAT CLSR Ch 8Ch
10h PXPCAP PXPNXTPTR PXPCAPID 90h
14h DEVCAP 94h
SUBBUS SECBUS PBUS 18h DEVSTS DEVCTRL 98h
SECSTS IOLIM IOBAS 1Ch LNKCAP 9Ch
MLIM MBAS 20h LNKSTS LNKCON A0h
PLIM PBAS 24h SLTCAP A4h
PBASU 28h SLTSTS SLTCON A8h
PLIMU 2Ch ROOTCAP ROOTCON ACh
30h ROOTSTS B0h
CAPPTR 34h DEVCAP2 B4h
38h DEVCTRL2 B8h
BCTRL INTPIN INTL 3Ch LNKCAP2 BCh
SNXTPTR SCAPID 40h LNKSTS2 LNKCON2 C0h
SDID SVID 44h
C4h
48h C8h
4Ch CCh
DMIRCBAR
1
Notes:
1. DMIRCBAR - Device 0 Only
50h
D0h
54h D4h
58h
D8h
5Ch
DCh
MSIMSGCTL MSINXTPTR MSICAPID 60h PMCAP E0h
MSGADR 64h PMCSR E4h
MSGDAT 68h
E8h
MSIMSK 6Ch ECh
MSIPENDING 70h F0h
74h F4h
78h F8h
7Ch FCh