Datasheet

Datasheet, Volume 2 429
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Processor Uncore Configuration Registers
4.2.14.15 RDIMMTIMINGCNTL2 Register
4.2.14.16 TCMRS—DDR3 MRS Timing Register
4.2.14.17 RD_ODT_TBL0—Read ODT Lookup Table 0 Register
One entry for each physical rank on each channel. Each entry defines which ODT
signals are asserted when accessing that rank. The register also includes ODT timing
control.
The recommended BIOS settings to keep the MC_TERM_RNK_MSK consistent are:
• Set Read ODT mapping – read ODT specifies all ODT pins assertion for a read
targeting at this rank. Clear read target DIMM’s termination rank bit. The non-
target DIMM’s termination rank bits must be set. All non-termination rank in the
ODT mapping table must be cleared.
RDIMMTIMINGCNTL2
Bus: 1 Device: 16 Function: 0 Offset: 240h
Bus: 1 Device: 16 Function: 1 Offset: 240h
Bus: 1 Device: 16 Function: 4 Offset: 240h
Bus: 1 Device: 16 Function: 5 Offset: 240h
Bit Attr
Reset
Value
Description
31:8 RV 0h Reserved
3:0 RW 5h
T_CKOFF
This field provides the tCKOFF timing parameter.
The number of tCK required for both DCKE0 and DCKE1 to remain LOW before
both CK/CK# are driven Low.
Minimum setting is 2.
TCMRS
Bus: 1 Device: 16 Function: 0 Offset: 244h
Bus: 1 Device: 16 Function: 1 Offset: 244h
Bus: 1 Device: 16 Function: 4 Offset: 244h
Bus: 1 Device: 16 Function: 5 Offset: 244h
Bit Attr
Reset
Value
Description
31:4 RV 0h Reserved
3:0 RW 8h
TMRD_DDR3
This field provides the DDR3 tMRD timing parameter. MRS to MRS minimum delay
in number of DCLK.
RD_ODT_TBL0
Bus: 1 Device: 16 Function: 0 Offset: 260h
Bus: 1 Device: 16 Function: 1 Offset: 260h
Bus: 1 Device: 16 Function: 4 Offset: 260h
Bus: 1 Device: 16 Function: 5 Offset: 260h
Bit Attr
Reset
Value
Description
31:30 RV 0h Reserved
29:24 RW 0h
RD_ODT_RANK3
Rank 3 Read ODT pins
23:22 RV 0h Reserved
21:16 RW 0h
RD_ODT_RANK2
Rank 2 Read ODT pins
15:14 RV 0h Reserved