Datasheet

Datasheet, Volume 2 427

Processor Uncore Configuration Registers
4.2.14.12 RPQAGE Register
This register allows the Read of Pending Queue Age Counters.
4.2.14.13 IDLETIME—Page Policy and Timing Parameter Register
At a high level, the goal of any page closing policy is to trade off some Premature Page
Closes (PPCs) in order to avoid more Overdue Page Closes (OPCs). In other words,
avoid costly Page Misses and turn them into Page Empties at the expense of
occasionally missing a Page Hit and instead getting a Page Empty. The processor
scheme achieves this by tracking the number of PPCs and OPCs over a certain
configurable window (of requests). It then compares the two values to configurable
thresholds, and adjusts the amount of time before closing pages accordingly.
RPQAGE
Bus: 1 Device: 16 Function: 0 Offset: 234h
Bus: 1 Device: 16 Function: 1 Offset: 234h
Bus: 1 Device: 16 Function: 4 Offset: 234h
Bus: 1 Device: 16 Function: 5 Offset: 234h
Bit Attr
Reset
Value
Description
31:26 RV 0h Reserved
25:16 RW 000h
IOCount
The name is misleading. Instead, it is RPQ Age Counter for the Medium and Low
priority (VC0) non-isoch transactions issued from HA. The counter is increased by
one every time there is a CAS command sent. When the RPQ Age Counter is equal
to this configured field value, the non-isoch transaction is aged to the next priority
level. BIOS must set this field to non-zero value before setting the
MCMTR.NORMAL=1. Recommended settings: 100h but subject to revision based
from post-silicon application specific performance tuning.
15:10 RV 0h Reserved
9:0 RW 000h
CPUGTCount
The name is misleading. Instead, it is RPQ Age Counter for the High priority (VCP)
transactions and Critical priority (VC1) isoch transactions issued from HA. The
counter is increased by one every time there’s a CAS command sent. When the
RPQ Age Counter is equal to this configured field value, the isoch transaction is
aged to the next priority level. BIOS must set this field to non-zero value before
setting the MCMTR.NORMAL=1. Recommended settings: 40h but subject to
revision based from post-silicon application specific performance tuning.
IDLETIME
Bus: 1 Device: 16 Function: 0 Offset: 238h
Bus: 1 Device: 16 Function: 1 Offset: 238h
Bus: 1 Device: 16 Function: 4 Offset: 238h
Bus: 1 Device: 16 Function: 5 Offset: 238h
Bit Attr
Reset
Value
Description
31:29 RV 0h Reserved
28 RW 1b
ADAPT_PG_CLSE
This register is programmed in conjunction with MCMTR.CLOSE_PG to enable
three different modes:
MCMTR.CLOSE_PG ADAPT_PG_CLSE Mode
00Open Page Mode
01Adaptive Open Mode
1 0 Closed Page Mode
1 1 Illegal
When ADAPT_PG_CLSE=0, the page close idle timer gets set with
IDLE_PAGE_RST_VAL times 4.