Datasheet

Processor Uncore Configuration Registers
426 Datasheet, Volume 2
4.2.14.10 TCSTAGGER_REF Register
This register provides the tRFC like timing constraint parameter except it is a timing
constraint applicable to REF-REF separation between different ranks on a channel.
Note: This register value only becomes effective after
MCMNT_UCR_CHKN_BIT.STAGGER_REF_EN is set.
4.2.14.11 TCMR0SHADOW—MR0 Shadow Register
MR0 Shadow Register
TCSTAGGER_REF
Bus: 1 Device: 16 Function: 0 Offset: 224h
Bus: 1 Device: 16 Function: 1 Offset: 224h
Bus: 1 Device: 16 Function: 4 Offset: 224h
Bus: 1 Device: 16 Function: 5 Offset: 224h
Bit Attr
Reset
Value
Description
31:10 RV 0h Reserved
9:0 RW 080h
T_STAGGER_REF
tRFC like timing constraint parameter except it is a timing constraint applicable to
REF-REF separation between different ranks on a channel.
It is recommended to set T_STAGGER_REF equal or less than the TRFC parameter
which is defined as:
0800 MT/s = 040h
1067 MT/s = 056h
1333 MT/s = 06Bh
1600 MT/s = 080h
1867 MT/s = 096h
TCMR0SHADOW
Bus: 1 Device: 16 Function: 0 Offset: 22Ch
Bus: 1 Device: 16 Function: 1 Offset: 22Ch
Bus: 1 Device: 16 Function: 4 Offset: 22Ch
Bus: 1 Device: 16 Function: 5 Offset: 22Ch
Bit Attr
Reset
Value
Description
31:12 RV 0h Reserved
11:0 RW 000h
MR0_SHADOW
BIOS programs this field for MR0 register A11:A0 for all DIMMs in this channel.
iMC hardware is dynamically issuing MRS to MR0 to control the fast and slow exit
PPD (MRS MR0 A12). Other address bits (A[11:0]) is defined by this register field.
A15:A13 are always zero.