Datasheet

Datasheet, Volume 2 425

Processor Uncore Configuration Registers
4.2.14.9 TCZQCAL—Timing Constraints ZQ Calibration Timing 
Parameter Register
14:12 RW 000b
MR2_SHDW_A7_SRT
Copy of MR2 A[7] shadow that defines per DIMM availability of SRT mode – set if
extended temperature range and ASR is not supported; otherwise, cleared.
Bit 14: DIMM 2
Bit 13: DIMM 1
Bit 12: DIMM 0
11 RV 0h Reserved
10:8 RW 000b
MR2_SHDW_A6_ASR
Copy of MR2 A[6] shadow which defines per DIMM availability of ASR mode – set
if Auto Self-Refresh (ASR) is supported; otherwise, cleared.
Bit 10: DIMM 2
Bit 9: DIMM 1
Bit 8: DIMM 0
7:6 RV 0h Reserved
5:0 RW 18h
MR2_SHDW_A5TO0
Copy of MR2 A[5:0] shadow
TCZQCAL
Bus: 1 Device: 16 Function: 0 Offset: 220h
Bus: 1 Device: 16 Function: 1 Offset: 220h
Bus: 1 Device: 16 Function: 4 Offset: 220h
Bus: 1 Device: 16 Function: 5 Offset: 220h
Bit Attr
Reset
Value
Description
31:16 RV 0h Reserved
15:8 RW 40h
T_ZQCS
tZQCS in DCLK cycles (32 to 255, default is 64)
7:0 RW 80h
ZQCSPERIOD
Time between ZQ-FSM initiated ZQCS operations in tREFI*128 (2 to 255, default
is 128).
Note: ZQCx is issued at SRX.
TCMR2SHADOW
Bus: 1 Device: 16 Function: 0 Offset: 21Ch
Bus: 1 Device: 16 Function: 1 Offset: 21Ch
Bus: 1 Device: 16 Function: 4 Offset: 21Ch
Bus: 1 Device: 16 Function: 5 Offset: 21Ch
Bit Attr
Reset
Value
Description