Datasheet

Processor Uncore Configuration Registers
424 Datasheet, Volume 2
4.2.14.7 TCSRFTP—Timing Constraints Self-Refresh Timing 
Parameter Register
4.2.14.8 TCMR2SHADOW—Timing Constraints MR2 Shadow Timing 
Parameter Register
TCSRFTP
Bus: 1 Device: 16 Function: 0 Offset: 218h
Bus: 1 Device: 16 Function: 1 Offset: 218h
Bus: 1 Device: 16 Function: 4 Offset: 218h
Bus: 1 Device: 16 Function: 5 Offset: 218h
Bit Attr
Reset
Value
Description
31:27 RW ch
T_MOD
Mode Register Set command update delay.
26 RV 0h Reserved
25:16 RW 100h
T_ZQOPER
Normal operation Full calibration time
15:12 RW Bh
T_XSOFFSET
tXS = T_RFC + 10 ns. Setup of T_XSOFFSET is number of cycles for 10 ns. Range
is between 3 and 11 DCLK cycles
11:0 RW 100h
T_XSDLL
Exit Self Refresh to commands requiring a locked DLL in the range of 128 to
4095 DCLK cycles
TCMR2SHADOW
Bus: 1 Device: 16 Function: 0 Offset: 21Ch
Bus: 1 Device: 16 Function: 1 Offset: 21Ch
Bus: 1 Device: 16 Function: 4 Offset: 21Ch
Bus: 1 Device: 16 Function: 5 Offset: 21Ch
Bit Attr
Reset
Value
Description
31:27 RV 0h Reserved
26:24 RW-LV 000b
ADDR_BIT_SWIZZLE
Each bit is set in case of the corresponding 2-rank UDIMM requires address
mirroring/swizzling. It indicates that some of the address bits are swizzled for
rank 1 (or rank 3), and this has to be considered in MRS command. The address
swizzling bits:
A3 and A4
A5 and A6
A7 and A8
BA0 and BA1
Bit 24 refers to DIMM 0
Bit 25 refers to DIMM 1
Bit 26 refers to DIMM 2
23:16 RW 02h
MR2_SHDW_A15TO8
Copy of MR2 A[15:8] shadow.
Bit 23-19: zero, copy of MR2 A[15:11], reserved for future JEDEC use
Bit 18-17: Rtt_WR; that is, copy of MR2 A[10:9]
Bit 16: zero, copy of MR2 A[8], reserved for future JEDEC use
15 RV 0h Reserved