Datasheet

Datasheet, Volume 2 423
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Processor Uncore Configuration Registers
4.2.14.5 TCRFP—Timing Constraints DDR3 Refresh Parameter Register
4.2.14.6 TCRFTP—Timing Constraints Refresh Timing Parameter Register
TCRFP
Bus: 1 Device: 16 Function: 0 Offset: 210h
Bus: 1 Device: 16 Function: 1 Offset: 210h
Bus: 1 Device: 16 Function: 4 Offset: 210h
Bus: 1 Device: 16 Function: 5 Offset: 210h
Bit Attr
Reset
Value
Description
31:16 RV 0h Reserved
15:12 RW 9h
REF_PANIC_WM
tREFI count level in which the refresh priority is panic (default is 9)
It is recommended to set the panic WM at least to 9, in order to utilize the
maximum no-refresh period possible
11:8 RW 8h
REF_HI_WM
tREFI count level that turns the refresh priority to high (default is 8)
7:0 RW 3Fh
OREFNI
Rank idle period that defines an opportunity for refresh, in DCLK cycles
TCRFTP
Bus: 1 Device: 16 Function: 0 Offset: 214h
Bus: 1 Device: 16 Function: 1 Offset: 214h
Bus: 1 Device: 16 Function: 4 Offset: 214h
Bus: 1 Device: 16 Function: 5 Offset: 214h
Bit Attr
Reset
Value
Description
31:25 RW 9h
T_REFIX9
This field indicates the minimum period between 9*T_REFI and tRAS maximum
(normally 70 us) in 1024 * DCLK cycles. The default value will need to reduce
100 DCLK cycles – uncertainty on timing of panic refresh.
24:15 RW 080h
T_RFC
Time of refresh from beginning of refresh until next ACT or refresh is allowed (in
DCLK cycles)
The recommended T_RFC for 2Gb DDR3 are:
0800 MT/s = 040h
1067 MT/s = 056h
1333 MT/s = 06Bh
1600 MT/s = 080h
1867 MT/s = 096h
14:0 RW 062Ch
T_REFI
Defines the average period between refreshes in DCLK cycles. This register
defines the 15b tREFI counter limit.
The recommended T_REFI[14:0] setting for 7.8 usec:
0800 MT/s = 0C30h
1067 MT/s = 1040h
1333 MT/s = 1450h
1600 MT/s = 1860h
1867 MT/s = 1C70h