Datasheet

Processor Uncore Configuration Registers
422 Datasheet, Volume 2
4.2.14.4 TCOTHP—Timing Constraints DDR3 Other Timing 
Parameter Register
TCOTHP
Bus: 1 Device: 16 Function: 0 Offset: 20Ch
Bus: 1 Device: 16 Function: 1 Offset: 20Ch
Bus: 1 Device: 16 Function: 4 Offset: 20Ch
Bus: 1 Device: 16 Function: 5 Offset: 20Ch
Bit Attr
Reset
Value
Description
31:28 RW 6h
t_cs_oe
Delay in Dclks to disable CS output after all CKE pins are low.
27:24 RW 6h
t_odt_oe
Delay in Dclks to disable ODT output after all CKE pins are low and either in self-
refresh or in IBTOff mode.
23:20 RW 2h
t_rwsr
Back to back READ to WRITE from same rank separation parameter. The actual
READ to WRITE command separation targeting same rank is:
TCDBP.T_CL – TCDBP.T_CWL + T_RWSR + 6 DCLKs
This is measured between the clock assertion edges of the two corresponding
asserted command CS#.
The maximum design range from the above calculation is 23.
19:16 RW 2h
t_rwdd
Back to back READ to WRITE from different DIMM separation parameter. The
actual READ to WRITE command separation is:
TCDBP.T_CL – TCDBP.T_CWL + T_RWDD + 6 DCLKs
This is measured between the clock assertion edges of the two corresponding
asserted command CS#.
The maximum design range from the above calculation is 23.
15:12 RW 2h
t_rwdr
Back to back READ to WRITE from different RANK separation parameter. The
actual READ to WRITE command separation is:
TCDBP.T_CL – TCDBP.T_CWL + T_RWDR + 6 DCLKs
This is measured between the clock assertion edges of the two corresponding
asserted command CS#.
The maximum design range from the above calculation is 23.
11 RW 0b
shift_odt_early
New in ES2:
This shifts the ODT waveform one cycle early relative to the timing set up in the
ODT_TBL2 register, when in 2N or 3N mode. This bit has no effect in 1N mode.
10:8 RW 0h
T_CWL_ADJ
This register defines additional WR data delay per channel in order to overcome
the WR-flyby issue. The total CAS write latency that the DDR sees is the sum of
T_CWL and the T_CWL_ADJ.
000 = no added latency (default)
001 = 1 Dclk of added latency
010 = 2 Dclk of added latency
011 = 3 Dclk of added latency
1xx = Reduced latency by 1 Dclk. Not supported at tCWL=5
7:5 RW 3h
T_XP
Exit Power Down with DLL on to any valid command; Exit Precharge Power Down
with DLL frozen to commands not requiring a locked DLL.
4:0 RW Ah
T_XPDLL
Exit Precharge Power Down with DLL frozen to commands requiring a locked DLL.