Datasheet

Datasheet, Volume 2 421

Processor Uncore Configuration Registers
2:0 RW 2h
T_RRDR
Back to back READ to READ from different RANK separation parameter. The actual
READ to READ command separation is:
T_RRDR + 5 DCLKs
This is measured between the clock assertion edges of the two corresponding
asserted command CS#.
Note: The minimum setting of the field must meet the DDRIO requirement for
READ to READ turnaround time to be at least 5 DClk at the DDRIO pin.
The maximum design range from the above calculation is 31.
TCRWP
Bus: 1 Device: 16 Function: 0 Offset: 208h
Bus: 1 Device: 16 Function: 1 Offset: 208h
Bus: 1 Device: 16 Function: 4 Offset: 208h
Bus: 1 Device: 16 Function: 5 Offset: 208h
Bit Attr
Reset
Value
Description