Datasheet

Processor Uncore Configuration Registers
420 Datasheet, Volume 2
4.2.14.3 TCRWP—Timing Constraints DDR3 Read Write Parameter 
Register
TCRWP
Bus: 1 Device: 16 Function: 0 Offset: 208h
Bus: 1 Device: 16 Function: 1 Offset: 208h
Bus: 1 Device: 16 Function: 4 Offset: 208h
Bus: 1 Device: 16 Function: 5 Offset: 208h
Bit Attr
Reset
Value
Description
31:30 RV 0h Reserved
29:27 RW 0h
T_CCD
Back to back CAS to CAS (that is, READ to READ or WRITE to WRITE) from same
rank separation parameter. The actual JEDEC CAS to CAS command separation is
(T_CCD + 4) DCLKs measured between the clock assertion edges of the two
corresponding asserted command CS#.
26:24 RW 2h Reserved
23:21 RW 2h
T_WRDD
Back to back WRITE to READ from different DIMM separation parameter. The
actual WRITE to READ command separation is:
TCDBP.T_CWL – TCDBP.T_CL + T_WRDD + 6 DCLKs
This is measured between the clock assertion edges of the two corresponding
asserted command CS#.
20:18 RW 2h
T_WRDR
Back to back WRITE to READ from different RANK separation parameter.The actual
WRITE to READ command separation is:
TCDBP.T_CWL – TCDBP.T_CL + T_WRDR + 6 DCLKs
This is measured between the clock assertion edges of the two corresponding
asserted command CS#.
17:15 RW 2h Reserved
14:12 RW 2h Reserved
11:9 RW 2h
T_WWDD
Back to back WRITE to WRITE from different DIMM separation parameter. The
actual WRITE to WRITE command separation is:
T_WWDD + 5 DCLKs
This is measured between the clock assertion edges of the two corresponding
asserted command CS#.
Note: te minimum setting of the field must meet the DDRIO requirement for
WRITE to WRITE turnaround time to be at least 6 DClk at the DDRIO pin.
The maximum design range from the above calculation is 15.
8:6 RW 2h
T_WWDR
Back to back WRITE to WRITE from different RANK separation parameter. The
actual WRITE to WRITE command separation is:
T_WWDR + 5 DCLKs
This is measured between the clock assertion edges of the two corresponding
asserted command CS#.
Note: The minimum setting of the field must meet the DDRIO requirement for
WRITE to WRITE turnaround time to be at least 6 DClk at the DDRIO pin.
The maximum design range from the above calculation is 15.
5:3 RW 2h
T_RRDD
Back to back READ to READ from different DIMM separation parameter. The actual
READ to READ command separation is:
T_RRDD + 5 DCLKs
This is measured between the clock assertion edges of the two corresponding
asserted command CS#.
Note: The minimum setting of the field must meet the DDRIO requirement for
READ to READ turnaround time to be at least 5 DClk at the DDRIO pin.
The maximum design range from the above calculation is 31.