Datasheet

Datasheet, Volume 2 419

Processor Uncore Configuration Registers
4.2.14.2 TCRAP—Timing Constraints DDR3 Regular Access 
Parameter Register
TCRAP
Bus: 1 Device: 16 Function: 0 Offset: 204h
Bus: 1 Device: 16 Function: 1 Offset: 204h
Bus: 1 Device: 16 Function: 4 Offset: 204h
Bus: 1 Device: 16 Function: 5 Offset: 204h
Bit Attr
Reset
Value
Description
31:30 RW 0h
CMD_STRETCH
This field defines the number of cycles the command is stretched.
00 = 1N operation
01 = Reserved
10 = 2N operation
11 = 3N operation
28:24 RW Ch
T_WR
WRITE recovery time (must be at least 15 ns equivalent)
23:22 RV 0h Reserved
21:16 RW 20h
T_FAW
Four activate window (must be at least 4*tRRD and at most 63)
15:12 RW 6h
T_WTR
DCLK delay from start of internal write transaction to internal read command
(must be at least the larger value of 4 DCLK or 7.5 ns)
iMC’s Write to Read Same Rank (T_WRSR) is automatically calculated based from
TCDBP.T_CWL + 4 + T_WTR.
11:8 RW 3h
T_CKE
CKE minimum pulse width (must be at least the larger value of 3 DCLK or 5 ns)
7:4 RW Ah
T_RTP
Internal READ Command to PRECHARGE Command delay, (must be at least the
larger value of 4 DCLK or 7.5 ns)
3RV0hReserved
2:0 RW 5h
T_RRD
ACTIVE to ACTIVE command period, (must be at least the larger value of 4 DCLK
or 6 ns)