Datasheet

Processor Uncore Configuration Registers
418 Datasheet, Volume 2
4.2.14 Integrated Memory Controller DIMM Channels 
Timing Registers
4.2.14.1 TCDBP—Timing Constraints DDR3 Bin Parameter Register
Note: T_AL register field has been removed in this release due to design complexity.
Throughout this document, T_AL has a constant zero value.
TCDBP
Bus: 1 Device: 16 Function: 0 Offset: 200h
Bus: 1 Device: 16 Function: 1 Offset: 200h
Bus: 1 Device: 16 Function: 4 Offset: 200h
Bus: 1 Device: 16 Function: 5 Offset: 200h
Bit Attr
Reset
Value
Description
31:27 RV 0h Reserved
26 RW 0b
cmd_oe_cs
Command/Address output enable follows CS output enable. Cmd_oe_on
overrides cmd_ow_cs
25 RW 0b
cmd_oe_on
Command/Address output enable always on.
24:19 RW 1Ch
T_RAS
ACT to PRE command period (must be at least 10, and at most 40)
18:14 RW 07h
T_CWL
CAS Write Latency (must be at least 5)
Note: tWL=tAL+tCWL
Programming Limitation: tCL - tWL can not be more than 4 DCLK cycles
13:9 RW 0Ah
T_CL
CAS Latency (must be at least 5)
Note: RL=tAL+tCL.
Programming Limitation: tCL - tWL can not be more than 4 DCLK cycles.
8:5 RW Ah
T_RP
PRE command period (must be at least 5)
4:0 RW 0Ah
T_RCD
ACT to internal read or write delay time in DCLK (must be at least 5)
Programming Limitation: T_RCD must be smaller than T_RAS