Datasheet
Processor Uncore Configuration Registers
416 Datasheet, Volume 2
4.2.13.17 PM_DLL—PM DLL Config Register
This register controls the master and slave DLL of the MC I/O.
The slave DLL, if configured to disable, is disabled when all ranks are in power-down.
The master DLL, if configured to disable, is disabled when self-refresh.
Both slave DLL and master DLL have wake-up time. Slave DLL disable has wake-up
time of ~50 ns, and master DLL wake-up time is ~500 ns. BIOS must programm with
the delay in DCLK cycles during power configuration or during the frequency change
flow. If the MDLL_sd_en or SDLL_sd_en is programmed to 0, this means that the
corresponding mode is disabled.
If IO channel disable option is disabled and master DLL is enabled, this means that in
power-down the slave IO channel disable remains active; but in self refresh both IO
channel disable and master DLL are shut-down.
Note: This register will be updated by BIOS only after reset. PCODE will sample this register
at the end of Phase 4. After this the register is assumed to remain unchanged.
PM_DLL
Bus: 1 Device: 16 Function: 0 Offset: 1DCh
Bus: 1 Device: 16 Function: 1 Offset: 1DCh
Bus: 1 Device: 16 Function: 4 Offset: 1DCh
Bus: 1 Device: 16 Function: 5 Offset: 1DCh
Bit Attr
Reset
Value
Description
31:19 RV 0h Reserved
17:16 RW 00b
MDLL_SDEN: Master DLL Shut-down Enable
00 = no DLL shut-down
Example - in 1.6 GHz, if DLL lock is 3 us (== 2400 DCLK cycles), the
DLL_W_timer should be set to 1888 DCLK cycles. In practice after DLL wakes-up,
it will count 1888 DCLK cycles until SR is exit, and another tXSDLL (typically
512 DCLK cycles) until the first data command is issued.
01 or 1X = Shut-down all MDLLs – command/control and data.
11:0 RW FFFh
MDLL_WTIMER: Master DLL Wake Up Timer (delay in DCLK)
Per DDRIO design input:
The MDLL lock time after the DLL Enable is issued, the lock time is about 100 ns at
1600 MHz and 200 ns at 800 MHz. It should be guardbanded to 500 ns. Thus, if
the wake up time from when the DLL enable is issued is counted, the wake up
time is 500 ns.
This field is defaulted to 533 MHz DCLK initial boot setting. BIOS need to
reprogram this register according to ~500 ns equivalent target speed. The
recommended setting for each DCLK speed is as follows:
DCLK (MHz) Setting
400 0C8h
533 10Bh
667 14Eh
800 190h
933 1D3h
1067 258h