Datasheet
Datasheet, Volume 2 415
Processor Uncore Configuration Registers
4.2.13.15 MC_TERM_RNK_MSK—MC Termination Rank Mask Register
4.2.13.16 PM_SREF—PM Self-Refresh Control Register
MC_TERM_RNK_MSK
Bus: 1 Device: 16 Function: 0 Offset: 1D4h
Bus: 1 Device: 16 Function: 1 Offset: 1D4h
Bus: 1 Device: 16 Function: 4 Offset: 1D4h
Bus: 1 Device: 16 Function: 5 Offset: 1D4h
Bit Attr
Reset
Value
Description
31:16 RW 01FFh
ch_ppds_idle_timer
PPDS idle counter after all rank’s rank idle counters (PDWN_IDEL_CNTR) have
been expired.
15:10 RV 0h Reserved
9:0 RW 111h
TERM_RNK_MSK
Physical Rank Mask to select which rank is used in the termination rank. BIOS
programs the PHYSICAL rank select for the termination rank from each DIMM. It is
important to note that this is the PHYSICAL CS# mapping instead of the LOGICAL
rank mapping.
Recommended Programming Method: Deciding and selecting the termination
rank on each populated DIMM. For simplicity, BIOS can always select rank 0 of
each populated DIMM as the termination rank unless rank 0 is marked as bad
rank.
Note: BIOS may also optionally enable rank interleaving to separate the
termination ranks and non-termination ranks so OS can map more frequently
used address ranges into the RIR with termination ranks while mapping less
frequently used address ranges into RIR with non-termination ranks. This
mapping enables a better power optimization to exploit our PPD-S capability.
BIOS must also keep RD_ODT_TBL0-2 and WR_ODT_TBL0-2 consistent. Refer to
those registers for further details.
This field CAN NOT be set as all zeros for populated channel. Minimum one
termination rank per DIMM. It has match rank occupancy for the ranks set as 1.
PM_SREF
Bus: 1 Device: 16 Function: 0 Offset: 1D8h
Bus: 1 Device: 16 Function: 1 Offset: 1D8h
Bus: 1 Device: 16 Function: 4 Offset: 1D8h
Bus: 1 Device: 16 Function: 5 Offset: 1D8h
Bit Attr
Reset
Value
Description
31:29 RV 0h Reserved
23:21 RV 0h Reserved
20 RW 0h
SREF_EN
Enable or disable opportunistic self-refresh mechanism.
19:0 RW FFFFFh
SREF_IDLE_CNTR
This field defines the rank idle period that causes self-refresh entrance. This value
is used when the ’SREFenable’ field is set. It defines the # of idle cycles after the
command issue; that there should not be any transaction in order to enter self-
refresh. It is programmable 1 to 1M-1 dynamically. In DCLK=800 MHz it
determines time of up to 1.3 ms. FFFFEh is a reserved value and should not be
used in normal operation.
The minimum setting needs to allow for a refresh, a zqcal, a retry read, and a
handful of cycles for the HA to issue a demand scrub write:
TCZQCAL.T_ZQCS + TCRFTP.T_RFC + 100 decimal. In reality, the idle counter
should be much larger to avoid unnecessary SRE+SRX overhead.
For Independent channel mode, this register field can be updated dynamically.