Datasheet

Processor Uncore Configuration Registers
414 Datasheet, Volume 2
26:25 RW 00b
Power Down Clock Modes for UDIMM
The field defines how CK and CK# are turned off during SR:
00 = CK_ON Mode: This mode defines the CK to be continue to be driven during
self-refresh.
01 = CK_TRI-STATE_AFTER_PULL_LOW_MODE: after tCKEoff timing delay from
SRE CKE de-assertion, iMC waits for tCKoff before dropping CK-ALIGN and
CK#-ALIGN (internal signal to DDRIO) to low. The CK-ALIGN and CK#-
ALIGN control the CK/CK# clock outputs directly. iMC waits for tCKEv before
de-asserting CKOutputEnable to DDRIO; that is, tri-stating CK, CK#. 
Note: DDRIO will have additional 5 QCLK delay of the CK/CK# tri-state.
Note: CKE signal tri-state is under separate control. All other drivers
(except DDR_RESET#) will be tri-stated.
10 = CK_PULL_LOW_MODE: after tCKEoff timing delay from SRE CKE de-
assertion, iMC waits for tCKoff before dropping CK-ALIGN and CK#-ALIGN
(internal signal to DDRIO) to LOW throughout the self-refresh. CKE tri-state
is under separate configuration control. All other signals (except
DDR_RESET#) are tri-stated after tCKEv delay.
11 = CK_PULL_HIGH_MODE: after tCKEoff timing delay from SRE CKE de-
assertion, iMC waits for tCKoff before pulling both CK-ALIGN and CK#-
ALIGN (internal signal to DDRIO) to HIGH throughout the self-refresh. CKE
tri-state is under separate configuration control. All other signals (except
DDR_RESET#) are tri-stated after tCKEv delay.
24 RW 0b
Enable IBT_OFF Register Power Down Mode
Enable IBT_OFF Register Power Down Mode when set; otherwise, IBT_ON is
enabled.
23:17 RV 0h Reserved
16 RW 0b
CKE Slow Exit (DLL-OFF) Mode
0 = Fast Exit; that is, DLL-ON
1 = Slow Exit; that is, DLL-OFF, PDWN_MODE_PPD (Bit 15) must be set if setting
this bit. MR0 for all non-termination ranks need to be set as PPD slow, where
MR0 for all termination ranks need to be set as PPD fast. IMC hardware will
dynamically update the MR0.A12 of the termination ranks upon entering/
exiting channel-level PPD-S.
This bit is set by BIOS during boot and it is unchanged after boot.
15 RW 0b
CKE Precharge Power Down Mode Enable
0 = PPD is disabled
1 = PPD is enabled
For Independent channel mode, this register field can be updated dynamically.
14 RW 0b
CKE Active Power Down Mode Enable
0 = APD is disabled
1 = APD is enabled
For Independent channel mode, this register field can be updated dynamically.
13:8 RV 0h Reserved
7:0 RW 80h
PDWN_IDLE_CNTR
This field defines the rank idle period that causes power-down entrance. The
number of idle cycles are based from command CS assertion. It is important to
program this parameter to be greater than roundtrip latency parameter in order to
avoid the CKE de-assertion sooner than data return.
For Independent channel mode, this register field can be updated dynamically.
PM_PDWN
Bus: 1 Device: 16 Function: 0 Offset: 1D0h
Bus: 1 Device: 16 Function: 1 Offset: 1D0h
Bus: 1 Device: 16 Function: 4 Offset: 1D0h
Bus: 1 Device: 16 Function: 5 Offset: 1D0h
Bit Attr
Reset
Value
Description