Datasheet

Datasheet, Volume 2 413
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Processor Uncore Configuration Registers
4.2.13.13 THRT_PWR_DIMM_[0:2]—THRT_PWR_DIMM_0 Register
bit[10:0]: Max number of transactions (ACT, READ, WRITE) to be allowed during the 1
usec throttling time frame per power throttling.
4.2.13.14 PM_PDWN—PM CKE OFF Control Register
THRT_PWR_DIMM_[0:2]
Bus: 1 Device: 16 Function: 0 Offset: 190h, 192h, 194h
Bus: 1 Device: 16 Function: 1 Offset: 190h, 192h, 194h
Bus: 1 Device: 16 Function: 4 Offset: 190h, 192h, 194h
Bus: 1 Device: 16 Function: 5 Offset: 190h, 192h, 194h
Bit Attr
Reset
Value
Description
15 RW 1b
THRT_PWR_EN
1 = Enable the power throttling for the DIMM.
14:12 RV 0h Reserved
11:0 RW FFFh
Power Throttling Control
This field indicates the maximum number of transactions (ACT, READ, WRITE) to
be allowed (per DIMM) during the 1 usec throttling time frame per power
throttling.
PCODE can update this register dynamically.
PM_PDWN
Bus: 1 Device: 16 Function: 0 Offset: 1D0h
Bus: 1 Device: 16 Function: 1 Offset: 1D0h
Bus: 1 Device: 16 Function: 4 Offset: 1D0h
Bus: 1 Device: 16 Function: 5 Offset: 1D0h
Bit Attr
Reset
Value
Description
31:30 RV 0h Reserved
29:28 RW 01b
PDWN_RDIMM_RC9_A4_A3
Bit 29 = Driven on DA4 during the RC9 control word access. Reserved in non-LR-
DIMM. In LR-DIMM, for LR-DIMM, DA4=1 for DQ clocking disable in CKE
power down.
Bit 28 = Driven on DA3 during the RC9 control word access. For non-LR-DIMM,
when set (default), register is in weak drive mode; otherwise, the
register is in float mode.
27 RW 0b
CKE output tri-state control during self-refresh
0 = CKE is not tri-stated during SR. UDIMM must have this bit set to 0.
1 = CKE is tri-stated during register clock off power down self-refresh.
This bit must set to zero if it is not doing register clock off power down self-
refresh.