Datasheet

Datasheet, Volume 2 411

Processor Uncore Configuration Registers
4.2.13.10 PM_CMD_PWR_[0:2]—Electrical Power and Thermal 
Throttling Command Power Register
PM_CMD_PWR_[0:2]
Bus: 1 Device: 16 Function: 0 Offset: 160h, 164h, 168h
Bus: 1 Device: 16 Function: 1 Offset: 160h, 164h, 168h
Bus: 1 Device: 16 Function: 4 Offset: 160h, 164h, 168h
Bus: 1 Device: 16 Function: 5 Offset: 160h, 164h, 168h
Bit Attr
Reset
Value
Description
31:27 RW 10h
ODT termination power weight
This field defines the number of DCLK of ODT-assertion to increase the OLTT and
ET energy counters (that is, corresponding PMSUMPCCXRY, ET_DIMMSUM and
ET_CH_SUM) by 16. Hardware provides internal ODT counters (two per DIMM
slot) to track each ODT. When the internal count decrement to zero, the
corresponding OLTT and ET energy counters are incremented by 16 and the
internal ODT counter is loaded with the content of this register field.
Possible Valid Range of the register field: 1–31. Others = Reserved.
Due to the energy accumulator width limitation, an additional programming
limitation is imposed – this field must be programmed equal to or greater than 4
DCLKs.
Programming below 4 is not validated and may jeopardize missing thermal event
or proper electrical/power throttling during certain corner cases due to energy
accumulator over-flow.
26:22 RW 10h
ACTIVE_IDLE_DIMM
This field defines the number of DCLK of CKE-assertion to increase the OLTT and
ET energy counters (that is, corresponding PMSUMPCCXRY, ET_DIMMSUM and
ET_CH_SUM) by 4. Hardware provides internal CKE counters (two per DIMM slot)
to track each CKE. When the internal count decrement to zero, the corresponding
OLTT and ET energy counters are increment by 4 and the internal CKE counter is
loaded with the content of this register field.
Valid Range of the register field : 1–31. Others = Reserved.
Due to the energy accumulator width limitation, an additional programming
limitation is imposed – this field must be programmed equal to or greater than 4
DCLKs
Programming below 4 is not validated and may jeopardize missing thermal event
or proper electrical/power throttling during certain corner cases due to energy
accumulator over-flow.
21:14 RW 00h
PWRREF_DIMM
Power contribution of 1x REF or SRE command. The 8b refresh weight defined
here is actually being multiplied by 8 (shift left by 3 bits) before being
accumulated in the electrical throttling and OLTT counters.
13:8 RW 0h
PWRACT_DIMM
Power contribution of ACT command in both OLTT and ET energy counters.
7:4 RW 0h
PWRCASW_DIMM
Power contribution of CAS WR/WRS4 command in both OLTT and ET energy
counters.
3:0 RW 0h
PWRCASR_DIMM
Power contribution of CAS RD/RDS4 command in both OLTT and ET energy
counters.