Datasheet

Processor Uncore Configuration Registers
410 Datasheet, Volume 2
4.2.13.9 DIMMTEMPSTAT_[0:2]—DIMM TEMP Status Register
DIMMTEMPSTAT_[0:2]
Bus: 1 Device: 16 Function: 0 Offset: 150h, 154h, 158h
Bus: 1 Device: 16 Function: 1 Offset: 150h, 154h, 158h
Bus: 1 Device: 16 Function: 4 Offset: 150h, 154h, 158h
Bus: 1 Device: 16 Function: 5 Offset: 150h, 154h, 158h
Bit Attr
Reset
Value
Description
31:29 RV 0h Reserved
28 RW1C 0b
Event Asserted on TEMPHI going HIGH
It is assumed that each of the event assertion is going to trigger Configurable
interrupt (Either MEMHOT# only or both SMI and MEMHOT#) defined in bit 30 of
ìCHN_TEMP_CFGî
27 RW1C 0b
Event Asserted on TEMPMID going High
It is assumed that each of the event assertion is going to trigger Configurable
interrupt (Either MEMHOT# only or both SMI and MEMHOT#) defined in bit 30 of
ìCHN_TEMP_CFGî
26 RW1C 0b
Event Asserted on TEMPLO Going High
It is assumed that each of the event assertion is going to trigger Configurable
interrupt (Either MEMHOT# only or both SMI and MEMHOT#) defined in bit 30 of
ìCHN_TEMP_CFGî
25 RW1C 0b
Event Asserted on TEMPOEMLO Going Low
It is assumed that each of the event assertion is going to trigger Configurable
interrupt (Either MEMHOT# only or both SMI and MEMHOT#) defined in bit 30 of
ìCHN_TEMP_CFGî
24 RW1C 0b
Event Asserted on TEMPOEMHI Going High
It is assumed that each of the event assertion is going to trigger Configurable
interrupt (Either MEMHOT# only or both SMI and MEMHOT#) defined in bit 30 of
ìCHN_TEMP_CFGî
23:8 RV 0h Reserved
7:0 RW-LV 55h
DIMM_TEMP
Current DIMM Temperature for thermal throttlingLock by
CLTT_DEBUG_DISABLE_LOCK
When the CLTT_DEBUG_DISABLE_LOCK is cleared (unlocked), debug software can
write to this byte to test various temperature scenarios.
When the CLTT_DEBUG_DISABLE_LOCK is set, this field becomes read-only; that
is, configuration write to this byte is aborted. This byte is updated from internal
logic from a 2:1 Multiplexing, which can be selected from either CLTT temperature
or from the corresponding uCR temperature registers output
(PCODE_TEMP_OUTPUT) updated from pcode. The mux select is controlled by
CLTT_OR_PCODE_TEMP_MUX_SEL defined in CHN_TEMP_CFG register.
Valid range from 0 to 127 (that is, 0 °C to +127 °C). Any negative value read from
TSOD is forced to 0. TSOD decimal point value is also truncated to integer value.
The default value is changed to 85 °C to avoid missing refresh during S3 resume
or during warm-reset flow after the DIMM is exiting self-refresh. The correct
temperature may not be fetched from TSOD yet but the DIMM temperature may
be still high and need to be refreshed at 2x rate.