Datasheet

Processor Uncore Configuration Registers
408 Datasheet, Volume 2
4.2.13.7 DIMM_TEMP_THRT_LMT_[0:2]—DIMM TEMP 
Configuration Register
All three THRT_CRIT, THRT_HI and THRT_MID are per DIMM BW limit; that is, all
activities (ACT, READ, WRITE) from all ranks within a DIMM are tracked together in one
DIMM activity counter.
DIMM_TEMP_THRT_LMT_[0:2]
Bus: 1 Device: 16 Function: 0 Offset: 130, 134, 138h
Bus: 1 Device: 16 Function: 1 Offset: 130, 134, 138h
Bus: 1 Device: 16 Function: 4 Offset: 130, 134, 138h
Bus: 1 Device: 16 Function: 5 Offset: 130, 134, 138h
Bit Attr
Reset
Value
Description
31:24 RV 0h Reserved
23:16 RW 00h
THRT_CRIT
Maximum number of throttled transactions (ACT, READ, WRITE) to be issued
during BWLIMITTF.
15:8 RW 0Fh
THRT_HI
Maximum number of throttled transactions (ACT, READ, WRITE) to be issued
during BWLIMITTF.
7:0 RW FFh
THRT_MID
Maximum number of throttled transactions (ACT, READ, WRITE) to be issued
during BWLIMITTF.