Datasheet
Datasheet, Volume 2 405
Processor Uncore Configuration Registers
4.2.13.3 CHN_TEMP_CFG—Channel TEMP Configuration Register
4.2.13.4 CHN_TEMP_STAT—Channel TEMP Status Register
CHN_TEMP_CFG
Bus: 1 Device: 16 Function: 0 Offset: 108h
Bus: 1 Device: 16 Function: 1 Offset: 108h
Bus: 1 Device: 16 Function: 4 Offset: 108h
Bus: 1 Device: 16 Function: 5 Offset: 108h
Bit Attr
Reset
Value
Description
31 RW 1h OLTT_EN: OLTT Temperature Tracking Enable
30 RV 0h Reserved
29 RW 0h
CLTT_OR_PCODE_TEMP_MUX_SEL
The TEMP_STAT byte update multiplexer select control to direct the source to
update DIMMTEMPSTAT_[0:3][7:0]:
0 = Corresponding to the DIMM TEMP_STAT byte from PCODE_TEMP_OUTPUT.
1 = TSOD temperature reading from CLTT logic.
28 RW-O 1b
CLTT_DEBUG_DISABLE_LOCK: lock bit of DIMMTEMPSTAT_[0:3][7:0]
Set this lock bit to disable configuration write to DIMMTEMPSTAT_[0:3][7:0].
When this bit is clear, system debug/test software can update the
DIMMTEMPSTAT_[0:3][7:0] to verify various temperature scenerios.
27 RW 1b Enables thermal bandwidth throttling limit
26:24 RV 0h Reserved
23:16 RW 00h
THRT_EXT
Maximum number of throttled transactions to be issued during BWLIMITTF due to
externally asserted MEMHOT#.
15 RW 0b
THRT_ALLOW_ISOCH
When this bit is zero, MC will lower CKE during Thermal Throttling, and ISOCH is
blocked. When this bit is one, MC will NOT lower CKE during Thermal Throttling,
and ISOCH will be allowed base on bandwidth throttling setting. However, setting
this bit would mean more power consumption due to CKE is asserted during
thermal or power throttling.
This bit can be updated dynamically in independent channel configuration only.
14:11 RV 0h Reserved
10:0 RW 3FFh
BW_LIMIT_TF
BW Throttle Window Size in DCLK
CHN_TEMP_STAT
Bus: 1 Device: 16 Function: 0 Offset: 10Ch
Bus: 1 Device: 16 Function: 1 Offset: 10Ch
Bus: 1 Device: 16 Function: 4 Offset: 10Ch
Bus: 1 Device: 16 Function: 5 Offset: 10Ch
Bit Attr
Reset
Value
Description
31:3 RV 0h Reserved
2RW1C0bEvent Asserted on DIMM ID 2
1RW1C0bEvent Asserted on DIMM ID 1
0RW1C0bEvent Asserted on DIMM ID 0