Datasheet

Processor Uncore Configuration Registers
404 Datasheet, Volume 2
4.2.13.2 ET_CFG—Electrical Throttling Configuration Register
ET_CFG
Bus: 1 Device: 16 Function: 0 Offset: 104h
Bus: 1 Device: 16 Function: 1 Offset: 104h
Bus: 1 Device: 16 Function: 4 Offset: 104h
Bus: 1 Device: 16 Function: 5 Offset: 104h
Bit Attr
Reset
Value
Description
31:16 RV 0h Reserved
15 RW 0h ET_EN: Electrical Throttling Enable
14:10 RV 0h Reserved
9:8 RW 1h
ET_DIV: Energy Equation Divider Control
00 = divider=2 (the energy counter is right shift by 1 bit)
01 = divider=4 (the energy counter is right shift by 2 bit)
10 = divider=8 (the energy counter is right shift by 3 bit)
11 = divider=16 (the energy counter is right shift by 4 bit)
7:0 RW 00h
ET_SMPL_PRD: Energy Calculation Sample Period (in number of DCLK)
This value is loaded onto the corresponding ETSAMPLEPERIOD count-down
counter. The counter is reload with the ETSAMPLEPERIOD count after it counted
zero.
When ET_EN is zero (disable electrical throttling), ET_SMPL_PRD should be set to
zero to avoid the corresponding SMI ET quiecense ack bit
(CH_FRZE_ET_CNTR_ACK) never asserted.
Recommended setting when ET_EN is enabled:
DCLK Setting
400 MHz 33h
533 MHz 44h
667 MHz 55h
800 MHz 66h
933 MHz 77h
However, the setting is subject to change per platform power delivery
recommendation.