Datasheet

Datasheet, Volume 2 403
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Processor Uncore Configuration Registers
4.2.12.46 RSP_FUNC_ADDR_MASK_HI Register
Complete address match (Addr[45:3]) and mask is supported for all HA writes. Error
injection does not use the response logic triggers and uses the match mask logic output
to determine which writes need to get error injection. Users can program up to two x4
device masks (8-bits per chunk – 64 bits per cacheline).
The address match function is gated by EPMCMAIN_DFX_LCK_CNTL.RSPLCK (uCR)
AND MC_ERR_INJ_LCK.MC_ERR_INJ_LCK (MSR) registers; that is, match operation
occurs only when either locks are cleared.
4.2.13 Integrated Memory Controller Thermal Control Registers
4.2.13.1 PXPCAP—PCI Express* Capability Register
RSP_FUNC_ADDR_MASK_HI
Bus: 1 Device: 15 Function: 2 Offset: 1CCh
Bus: 1 Device: 15 Function: 3 Offset: 1CCh
Bus: 1 Device: 15 Function: 4 Offset: 1CCh
Bus: 1 Device: 15 Function: 5 Offset: 1CCh
Bit Attr
Reset
Value
Description
31:24 RV 0h Reserved
15:11 RV 0h Reserved
10:0 RWS 000h
ADDR_MASK_HIGHER
Address Mask to deselect (when set) the corresponding Addr[45:35] for the
address match.
PXPCAP
Bus: 1 Device: 16 Function: 0 Offset: 40h
Bus: 1 Device: 16 Function: 1 Offset: 40h
Bus: 1 Device: 16 Function: 4 Offset: 40h
Bus: 1 Device: 16 Function: 5 Offset: 40h
Bit Attr
Reset
Value
Description
31:30 RV 0h Reserved
29:25 RO 00h
Interrupt Message Number
Not applicable for this device
24 RO 0b
Slot Implemented
Not applicable for integrated endpoints
23:20 RO 9h
Device/Port Type
Device type is Root Complex Integrated Endpoint
19:16 RO 1h
Capability Version
PCI Express Capability is Compliant with Version 1.0 of the PCI Express
specification.
Note: This capability structure is not compliant with Versions beyond 1.0, since
they require additional capability registers to be reserved. The only purpose for
this capability structure is to make enhanced configuration space available.
Minimizing the size of this structure is accomplished by reporting version 1.0
compliancy and reporting that this is an integrated root port device. As such, only
three DWords of configuration space are required for this structure.
15:8 RO 00h
Next Capability Pointer
Pointer to the next capability. Set to 0 to indicate there are no more capability
structures.
7:0 RO 10h
Capability ID
Provides the PCI Express capability ID assigned by PCI-SIG.