Datasheet

Datasheet, Volume 2 401

Processor Uncore Configuration Registers
4.2.12.42 RIRILV7OFFSET_4—RIR Range Rank Interleave 7 
OFFSET Register
4.2.12.43 RSP_FUNC_ADDR_MATCH_LO Register
Complete address match (Addr[45:3]) and mask is supported for all HA
writes. Instead of using DFx global response logic triggers, the error injection
logic uses the address match mask logic output to determine which memory
writes need to get error injection. Users can program up to two x4 device
masks (8-bits per chunk – 64 bits per cacheline).
RIRILV7OFFSET_4
Bus: 1 Device: 15 Function: 2 Offset: 1BCh
Bus: 1 Device: 15 Function: 3 Offset: 1BCh
Bus: 1 Device: 15 Function: 4 Offset: 1BCh
Bus: 1 Device: 15 Function: 5 Offset: 1BCh
Bit Attr
Reset
Value
Description
31:20 RV 0h Reserved
19:16 RW-LB 0h
RIR_RNK_TGT7
Target rank ID for rank interleave 7 (used for 1/2/4/8-way RIR interleaving).
15 RV 0h Reserved
14:2 RW-LB 0h
RIR_OFFSET7
RIR[5:0].RANKOFFSET7[38:26] == rank interleave 0 offset, 64 MB granularity
(processor’s minimum rank size is 512 MB. 512 MB/8 interleave = 64 MB per 8-
way interleave.)
1:0 RV 0h Reserved
RSP_FUNC_ADDR_MATCH_LO
Bus: 1 Device: 15 Function: 2 Offset: 1C0h
Bus: 1 Device: 15 Function: 3 Offset: 1C0h
Bus: 1 Device: 15 Function: 4 Offset: 1C0h
Bus: 1 Device: 15 Function: 5 Offset: 1C0h
Bit Attr
Reset
Value
Description
31:0 RWS
000000
00h
ADDR_MATCH_LOWER
Addr Match Lower: 32-bits (Match Addr[34:3])